參數(shù)資料
型號(hào)： RTL8305SB
英文描述： RTL8305SB
中文描述： RTL8305SB
文件頁(yè)數(shù)： 34/66頁(yè)
文件大?。?/td> 963K
代理商： RTL8305SB
RTL8305SB
2002/04/09
34
Rev.1.0
External MAC interface:
In order to act as PHY. When port4 is in PHY mode, some pins of the external MAC interface
should be changed. For example, TXC are input pins for MAC but output pins for PHY. So the pin MTXC/PRXC is input for
MAC mode and output for PHY mode. Please refer to below diagram to check the relationship between RTL8305SB and the
external device. Hint: Connect input of RTL8305SB to output of external device. RTL8305SB has no RXER, TXER, and CRS
pins for MII signaling. Because RTL8305SB does not support pin CRS, it is necessary to connect the MTXEN/PRXDV
(output) of PHY mode to both CRS and RXDV (input) of the external device.
Note: In order to differentiate between MAC and PHY mode, the RTL8305SB change the pin name of PHY mode. For example:
RTL8305SB=MRXD[0]/PTXD[0], RTL8305S=MRXD[0]/MTXD[0].
Port4 status pins:
When P4MODE[1:0]=11, Port4 can be either UTP or MAC mode MII. Port4 will automatically detect the
link status of UTP from internal PHY and link status MAC mode MII from both TXC of external PHY and P4LNKSTA#. If
both UTP and MII port are linked OK, UTP has higher priority and RTL8305SB will ignore the signal of MII port.
In UTP and FX mode, the internal PHY will provide the port status (Link/Speed/Duplex/Full Flow Control ability) in real time.
In order to provide the initial configuration of Port4’s PHY (UTP or FX mode), four pins (P4ANEG, P4Full, P4Spd100,
P4EnFC) are used to strap upon reset.
Upon reset:
defined as a short time after at the end of hardware reset. However, three of
these pins are also used for Port4’s MAC (the other three modes) in real time after reset (P4Spd100 -> P4SpdSta, P4Full ->
P4DupSta, P4EnFC -> P4FLCTRL).
After reset:
defined as the time after upon reset.
Note: These 3 pin are changed as high
active in order to provide dual function. For example: RTL8305SB=P4SpdSta/P4Spd100, RTL8305SB=P4SpdSta#.
In the other three modes, four pins (P4LNKSTA#, P4SpdSta, P4DupSta, P4FLCTRL) are necessary in order to provides the
port status to Port4’s MAC in real time. That means that the external MAC or PHY should be forced to the same port status as
Port4’s MAC.
Related pins:
When port4 is in UTP or FX mode, the LEDs of port4 are used to displays PHY status. When port4 is in other
mode, the LEDs of port4 are used to displays MAC status.
Four parallel LEDs corresponding to port 4 can be three-stated (disable LED functions) for MII port application by setting
ENP4LED in EEPROM as 0. In UTP application, this bit should be 1 to drive LEDs of port 4.
Pin
SEL_MIIMAC#
can be used to indicate MII MAC port active after reset for the sake of UTP/MII auto-detection.
One 25MHz clock output (pin CK25MOUT) can be used as a clock source of the underlying HomePNA/other PHY physical
devices.
Note: the output voltage is 2.5V for RTL8305SB but is 3.3V for RTL8305S.
PHY mode MII/PHY mode SNI:
In routing application, RTL8305SB cooperates with a routing engine to communicate with
WAN (Wide Area Network) through MII/SNI. In such application, P4LNKSTA# =0 and P4MODE[1] is pulled low upon reset.
P4MODE[0] determines whether MII or SNI mode is selected.
In MII (nibble) mode (P4MODE[0]=1), P4SPDSTA=1 results in MII operating at 100Mbps with MTXC and MRXC runs at
25MHz; however, P4SPDSTA=0 leads to MII operating at 10Mbps with MTXC and MRXC runs at 2.5MHz.
In SNI (serial) mode (P4MODE[0]=0), P4SPDSTA takes no effect and should be pull-down. SNI mode operates at 10Mbps
only, with MTXC and MRXC running at 10MHz. In SNI mode, RTL8305SB does not loopback RXDV signal as response to
TXEN and does not support heart-beat function. (asserting COL signal for each complete of TXEN signal).
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