參數(shù)資料
型號(hào)： RG82870P2
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 146/157頁
文件大?。?/td> 1407K
代理商： RG82870P2
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
89
R
3.8.4.
PCISTS1 – PCI-PCI Status Register – Device #1
Address Offset:
06-07h
Default Value:
00A0h
Access:
Read Only, Read/Write Clear
Size:
16 bits
PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with primary
side of the “virtual” PCI-PCI bridge embedded within the MCH-M. Since this device does not
physically reside on PCI_A it reports the optimum operating conditions so that it does not restrict the
capability of PCI_A.
Bit
Descriptions
15
Detected Parity Error (DPE1): Not Applicable - hardwired to “0.”
14
Signaled System Error (SSE1): This bit is set to 1 when MCH-M Device #1 generates an SERR
message over the hub interface A for any enabled Device #1 error condition. Device #1 error
conditions are enabled in the ERRCMD, PCICMD1 and BCTRL1 registers. Device #1 error flags are
read/reset from the ERRSTS and SSTS1 register. Software clears this bit by writing a 1 to it.
13
Received Master Abort Status (RMAS1): Not Applicable - hardwired to “0.”
12
Received Target Abort Status (RTAS1): Not Applicable - hardwired to “0.”
11
Signaled Target Abort Status (STAS1): Not Applicable - hardwired to “0.”
10:9
DEVSEL# Timing (DEVT1): This bit field is hardwired to “00b” to indicate that the device #1 uses the
fastest possible decode.
8
Data Parity Detected (DPD1): Not Applicable - hardwired to “0”.
7
Fast Back-to-Back Capable (FB2B1): This bit is hardwired to “1” to indicate that the AGP port
supports fast back to back transactions when the transactions are to different targets.
6
Reserved
5
66-MHz Capability (CAP66): This bit is hardwired to “1” to indicate that the AGP port is 66-MHz
capable.
4:0
Reserved
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