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參數(shù)資料
| 型號(hào)： | RG82870P2 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 12/157頁(yè) |
| 文件大?。?/td> | 1407K |
| 代理商： | RG82870P2 |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
109
R
4.1.5.
System Bus Interrupt APIC Memory Space
SBINTR
From
0_FEE0_0000
To
0_FEEF_FFFF
The System Bus interrupt space is the address used to deliver interrupts to the system bus. Any device on
AGP or hub interface, D, E may issue a Memory Write to 0FEEx_xxxxh. The MCH-M will forward this
Memory Write along with the data to the system bus as an Interrupt Message Transaction. The MCH-M
terminates the system bus transaction by providing the response and asserting TRDY#. This Memory
Write cycle does not go to DRAM.
4.1.6.
High SMM Memory Space
HIGHSMM
From
0_FEDA_0000
To
0_FEDB_FFFF
The HIGHSMM space allows cacheable access to the compatible SMM space by re-mapping valid SMM
accesses between 0_FEDA_0000 and 0_FEDB_FFFF to accesses between 0_000A_0000 and
0_000B_FFFF. The accesses are remapped when SMRAM space is enabled, an appropriate access is
detected on the system bus, and when ESMRAMC.H_SMRAME allows access to high SMRAM space.
SMM memory accesses from any hub interface or AGP are specially terminated: reads are provided with
the value from address 0 while writes are ignored entirely.
4.1.7.
AGP Aperture Space (Device #0 BAR)
AGPAPP
From
APBASE
To
APBASE + APSIZE
Processors and AGP devices communicate through a special buffer called the “graphics aperture”. This
aperture acts as a window into the main DRAM memory and is defined by the APBASE and APSIZE
configuration registers of the Intel 845MP/845MZ Chipset MCH-M. Note that the AGP aperture must be
above the top of memory and must not intersect with any other address space.
4.1.8.
AGP Memory and Prefetchable Memory
M1
From
MBASE1
To
MLIMIT1
PM1
PMBASE1
PMLIMIT1
Plug-and-play software configures the AGP memory window in order to provide enough memory space
for the devices behind this PCI-to-PCI bridge. Accesses whose addresses fall within this window are
decoded and forwarded to AGP for completion. Note that these registers must be programmed with
values that place the AGP memory space window between the value in the TOM register and 4 GB. In
addition, neither region should overlap with any other fixed or relocatable area of memory.
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