參數(shù)資料
型號(hào): RG82845MP
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù): 96/157頁
文件大小: 1407K
代理商: RG82845MP
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
43
R
3.6.1.
DRAMWIDTH—DRAM Width Register
Address Offset:
2Ch
Default Value:
00h
Access:
R/W
Size:
8 bits
This register determines the width of SDRAM devices populated in each row of memory.
Bit
Descriptions
7:4
Reserved.
3
Row 3 Width. Width of devices in Row 3
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
2
Row 2 Width. Width of devices in Row 2
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
1
Row 1 Width. Width of devices in Row 1
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
0
Row 0 Width. Width of devices in Row 0
0 = 16-bit wide devices, or Unpopulated (default)
1 = 8-bit wide devices
Note: Since there are multiple clock signals assigned to each row of a DIMM, it is important to clarify exactly
which row width field affects which clock signal.
Row Parameters
DDR Clocks Affected
0
SCK[2:0]/SCK[2:0]#
1
SCK[2:0]/SCK[2:0]#
2
SCK[5:3]/SCK[5:3]#
3
SCK[5:3]/SCK[5:3]#
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