- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄225036 > RG82845MP Controller Miscellaneous - Datasheet Reference PDF資料下載
參數(shù)資料
| 型號： | RG82845MP |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 139/157頁 |
| 文件大?。?/td> | 1407K |
| 代理商： | RG82845MP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁當前第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
82
Datasheet
250687-002
R
3.7.36.
ERRCMD – Error Command Register – Device #0
Address Offset:
CA-CBh
Default Value:
0000h
Access:
Read Only, Read/Write
Size:
16 bits
This register enables various errors to generate an SERR message via the hub interface A. Since the
MCH-M does not have an SERR# signal, SERR messages are passed from the MCH-M to the ICH3-M
over the hub interface. When a bit in this register is set, an SERR message will be generated on hub
interface whenever the corresponding flag is set in the ERRSTS register. The actual generation of the
SERR message is globally enabled for Device #0 via the PCI Command register.
Note: An error can generate one and only one error message via the hub interface A. It is software’s
responsibility to make sure that when an SERR error message is enabled for an error condition; SMI and
SCI error messages are disabled for that same error condition.
Bit
Description
15:10
Reserved
9
SERR on Non-DRAM Lock (LCKERR): When this bit is asserted, the MCH-M will generate a hub
interface A SERR special cycle whenever a processor lock cycle is detected that does not hit DRAM
8:7
Reserved
6
SERR on Target Abort on hub interface A Exception (TAHLA_SERR): When this bit is set, the
generation of the hub interface A SERR message is enabled when an MCH-M originated hub
interface A cycle is completed with “Target Abort” completion packet or special cycle status.
5
SERR on Detecting Hub Interface A Unimplemented Special Cycle (HIAUSCERR): When this bit
is set to 1 the MCH-M generates an SERR message over hub interface A when an Unimplemented
Special Cycle is received on the hub interface. When this bit is set to 0 the MCH-M does not generate
an SERR message for this event. SERR messaging for Device 0 is globally enabled in the PCICMD
register.
4
SERR on AGP Access Outside of Graphics Aperture (OOGF_SERR): When this bit is set, the
generation of the hub interface A SERR message is enabled when an AGP access occurs to an
address outside of the graphics aperture.
3
SERR on Invalid AGP Access (IAAF_SERR): When this bit is set, the generation of the hub
interface A SERR message is enabled when an AGP access occurs to an address outside of the
graphics aperture and either to the 640K - 1M range or above the top of memory.
2
SERR on Invalid Translation Table Entry (ITTEF_SERR): When this bit is set, the generation of the
hub interface A SERR message is enabled when an invalid translation table entry was returned in
response to an AGP access to the graphics aperture.
1
SERR Multiple-Bit DRAM ECC Error (DMERR_SERR): When this bit is set, the generation of the
hub interface A SERR message is enabled when the MCH-M DRAM controller detects a multiple-bit
error. For systems not supporting ECC this bit must be disabled.
0
SERR on Single-bit ECC Error (DSERR): When this bit is set, the generation of the hub interface A
SERR message is enabled when the MCH-M DRAM controller detects a single bit error. For systems
that do not support ECC this bit must be disabled.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RG82845MZ | Controller Miscellaneous - Datasheet Reference |
| RG82870P2 | Controller Miscellaneous - Datasheet Reference |
| RH5RE36AA-T1-FA | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
| RH5RE56AA-T1-FA | 5.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
| RE5RE36AA-TZ-FC | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PBCY3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RG82845MP S L66J | 制造商:Intel 功能描述:Chipset Memory Controller Hub Mobile 593-Pin FCBGA |
| RG82845MZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| RG82845PE S L6H5 | 制造商:Intel 功能描述:CHIPSTGMCH 82845PE HT-PBGA760 |
| RG82845PESL6Q3 | 制造商:Intel 功能描述:Chipsets |
| RG82845-SL5V7 | 制造商:Intel 功能描述:INTEL 845G GRAPHICS AND MEMORY CONTROLLER HUB(GMCH) |
發(fā)布緊急采購，3分鐘左右您將得到回復。