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| 型號(hào)： | RG82845MP |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 25/157頁(yè) |
| 文件大小： | 1407K |
| 代理商： | RG82845MP |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
120
Datasheet
250687-002
R
Memory writes originating from the host or from the hub interface use the Fast Write protocol when it is
both capability enabled and enabled. The data rate used to perform the Fast Writes is dependent on the
bits set in the AGP Command Register bits 2:0 (DATA_RATE). If bit 2 of the
AGPCMD[DATA_RATE] field is 1, the data transfers occur using 4x strobing. If bit 1 of
AGPCMD[DATA_RATE] field is 1, the data transfers occur using 2x strobing. If bit 0 of
AGPCMD[DATA_RATE] field is 1, Fast Writes are disabled and data transfers occur using standard
PCI protocol. Note that only one of the three DATA_RATE bits may be set by initialization software.
This is summarized in the following table.
Table 30. Fast Write Initialization
FWEN
DATA_RATE
[2]
DATA_RATE
[1]
DATA_RATE
[0]
MCH-M =>AGP Master Write
Protocol
0
X
x
1x
1
0
1
1x
1
0
1
0
2x Strobing
1
0
4x Strobing
5.3.6.
AGP FRAME# Transactions on AGP
The MCH-M accepts and generates AGP FRAME# transactions on the AGP bus. The MCH-M
guarantees that AGP FRAME# accesses to DRAM are kept coherent with the processor caches by
generating snoops to the host bus. LOCK#, SERR#, and PERR# signals are not supported.
5.3.6.1.
MCH-M Target and Initiator Operations for AGP FRAME# Transactions
The following table summarizes MCH-M target operation for AGP FRAME# initiators. The only cycles
that will be claimed are memory accesses to main memory.
Table 31. PCI Commands Supported by the MCH-M When Acting as a FRAME# Target
MCH-M
PCI Command
C/BE[3:0]# Encoding
Cycle Destination
Response as aFRAME#
Target
Interrupt Acknowledge
0000
N/A
No Response
Special Cycle
0001
N/A
No Response
I/O Read
0010
N/A
No Response
I/O Write
0011
N/A
No Response
Reserved
0100
N/A
No Response
Reserved
0101
N/A
No Response
Memory Read
0110
Main Memory
Read
0110
The Hub interface
No Response
Memory Write
0111
Main Memory
Post Data
0111
The Hub interface
No Response
Reserved
1000
N/A
No Response
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RG82845MZ | Controller Miscellaneous - Datasheet Reference |
| RG82870P2 | Controller Miscellaneous - Datasheet Reference |
| RH5RE36AA-T1-FA | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
| RH5RE56AA-T1-FA | 5.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSSO3 |
| RE5RE36AA-TZ-FC | 3.6 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PBCY3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RG82845MP S L66J | 制造商:Intel 功能描述:Chipset Memory Controller Hub Mobile 593-Pin FCBGA |
| RG82845MZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| RG82845PE S L6H5 | 制造商:Intel 功能描述:CHIPSTGMCH 82845PE HT-PBGA760 |
| RG82845PESL6Q3 | 制造商:Intel 功能描述:Chipsets |
| RG82845-SL5V7 | 制造商:Intel 功能描述:INTEL 845G GRAPHICS AND MEMORY CONTROLLER HUB(GMCH) |
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