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參數(shù)資料
| 型號： | RG82845MP |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 18/157頁 |
| 文件大?。?/td> | 1407K |
| 代理商： | RG82845MP |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
114
Datasheet
250687-002
R
5.
Functional Description
5.1.
Host Interface Overview
The Intel 845MP/845MZ Chipset MCH-M supports the Mobile Intel Pentium 4 Processor-M at 100-
MHz bus frequency; the address signals run at 200 MT/s for a maximum address queue rate of 50M
addresses/sec. The data is quad pumped and an entire 64B cache line can be transferred in two bus
clocks. At 100-MHz bus frequency, the data signals run at 400 MT/s for a maximum bandwidth of 3.2
GB/s. A 12-deep IOQ is supported by the 845MP/845MZ Chipset.
The Intel 845MP/845MZ Chipset MCH-M supports two outstanding deferred transactions on the system
bus. The two transactions must target different IO interfaces as only one deferred transaction can be
outstanding to any single IO interface at a time.
5.1.1.
Dynamic Bus Inversion
The Intel 845MP/845MZ Chipset MCH-M supports Dynamic Bus Inversion (DBI) when driving, and
when receiving data from the Host Bus. DBI limits the number of data signals that are driven to a low
voltage on each quad pumped data phase. This decreases the power consumption of the MCH-M.
DINV[3:0]# indicates if the corresponding 16 bits of data are inverted on the bus for each quad pumped
data phase:
Table 27. Relation of DBI Bits to Data Bits
DINV[3:0]#
Data Bits
DBI0#
HD[15:0]#
DIBI1#
HD[31:16]#
DBI2#
HD[47:32]#
DBI3#
HD[63:48]#
Whenever the CPU or the MCH-M drives data, each 16-bit segment is analyzed. If more than 8 of the 16
signals would normally be driven low on the bus the corresponding DBI# signal will be asserted and the
data will be inverted prior to being driven on the bus. Whenever the CPU or the MCH-M receives data it
monitors DBI[3:0]# to determine if the corresponding data segment should be inverted.
5.1.2.
System Bus Interrupt Delivery
The Mobile Intel Pentium 4 Processor-M supports System Bus interrupt delivery, but they do not support
the APIC serial bus interrupt delivery mechanism. Interrupt related messages are encoded on the System
Bus as “Interrupt Message Transactions”. In an Intel 845MP/845MZ Chipset platform, System Bus
interrupts may originate from the processor on the System Bus, or from a downstream device on hub
interface, or AGP. In the later case the MCH-M drives the “Interrupt Message Transaction” onto the
System Bus.
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