
R01UH0218EJ0110 Rev.1.10
Page 130 of 664
Sep 12, 2011
R32C/142 Group and R32C/145 Group
7. Clock Generator
7.7.2.3
Pin State in Wait Mode
Table 7.4 lists the pin state in wait mode.
7.7.2.4
Exiting Wait Mode
The MCU exits wait mode by a hardware reset, an NMI, or a peripheral interrupt assigned to software
interrupt number from 0 to 63.
To exit wait mode using either a hardware reset or NMI, without using peripheral interrupts, bits ILVL2 to
ILVL0 for the peripheral interrupts should be set to 000b (interrupt disabled) before executing the WAIT
instruction.
The CM02 bit setting in the CM0 register affects the peripheral interrupts. When the CM02 bit is set to 0
(peripheral clock source not stopped in wait mode), peripheral interrupts for software interrupt numbers
from 0 to 63 can be used to exit wait mode. When this bit is set to 1 (peripheral clock source stopped in
wait mode), peripheral functions operated using clocks (f1, f8, f32, f2n whose clock source is the
peripheral clock source, and fAD) generated by the peripheral clock source stop operating. Therefore,
the peripheral interrupts cannot be used to exit wait mode. However, peripheral functions operated
using clocks which are independent from the peripheral clock source (fC32, external clock, and f2n
whose clock source is the main clock) do not stop operating. Thus, interrupts generated by peripheral
functions and assigned to software interrupt numbers from 0 to 63 can be used to exit wait mode.
The CPU clock used when exiting wait mode by a peripheral interrupt or an NMI is the same clock used
when the WAIT instruction is executed.
Table 7.5 lists interrupts used to exit wait mode and usage conditions.
Table 7.4
Pin State in Wait Mode
Pin
State in Wait Mode
Ports
The state immediately before entering wait mode is held
DA0, DA1
The state immediately before entering wait mode is held
CLKOUT
When a low
speed clock is
selected
The clock is output
When f8 or f32
is selected
The clock is output when the CM02 bit in the CM0 register is set to 0 (no
peripheral clock source stopped in wait mode).
The state immediately before entering wait mode is held when the CM02
bit is set to 1 (peripheral clock source stopped in wait mode)