
R01UH0218EJ0110 Rev.1.10
Page 114 of 664
Sep 12, 2011
R32C/142 Group and R32C/145 Group
7. Clock Generator
The following sections illustrate clocks generated in clock generators.
7.1.1
Main Clock
The main clock is generated by the main clock oscillator. This clock can be a clock source for the PLL
reference clock or peripheral clocks. It also functions as an operating clock for the CAN module.
The main clock oscillator is configured with two pins, XIN and XOUT, connected by an oscillator or
resonator. The circuit has an on-chip feedback resistor which is separated from the oscillator in stop
mode to save power consumption. An external clock can be applied to the XIN pin in this circuit.
Figure7.11 shows an example of a main clock circuit connection.
Circuit constants vary depending on the oscillator. Circuit constants should be set as per the oscillator
manufacturer’s recommendations.
After a reset, the main clock oscillator is still independently active and disconnected from the PLL
frequency synthesizer. A PLL frequency synthesizer self-oscillating clock divided by 12 is provided to
the CPU.
Setting the CM05 bit in the CM0 register to 1 (main clock oscillator disabled) enables power-saving. In
this case, the clock applied to the XOUT pin becomes high. The XIN pin connected to the XOUT pin by
an embedded feedback resistor is also driven high. When an external clock is applied to the XIN pin,
the CM05 bit should not be set to 1.
All clocks, including the main clock, stop in stop mode. Refer to
7.7 “Power Control” for details.
Figure 7.11
Main Clock Circuit Connection
XIN
XOUT
CIN
COUT
Oscillator
Rd (1)
MCU
(feedback resistor embedded)
XIN
XOUT
MCU
(feedback resistor embedded)
External clock
Open
VCC
VSS
Note:
1. Insert a damping resistor if required. Resistance values may vary according to oscillator setting. Values
recommended by the manufacturer should be set. A feedback resistor should be placed between XIN
and XOUT if the manufacturer recommends placing a resistor externally.