
R01UH0218EJ0110 Rev.1.10
Page 178 of 664
Sep 12, 2011
R32C/142 Group and R32C/145 Group
12. DMAC
Notes:
1.
The falling edge and both edges of signals applied to the
INTi pin (i = 0 to 3) become the DMA
request sources. These request sources are not affected by external interrupts (the IFSR0 register
and bits POL and LVS in the INTiIC register), and vice versa.
2.
Registers UiSMR and UiSMR2 (i = 0 to 2) are used to switch between the UARTi receive interrupt
and ACK interrupt.
Table 12.2
DMiSL Register (i = 0 to 3) Functions
Setting Value
DMA Request Source
b4 b3 b2 b1 b0
DMA0
DMA1
DMA2
DMA3
0 0 0 0 0 Select from DMiSL2 register
0 0 0 0 1 Falling edge of
INT0
(1) Falling edge of INT1
(1) Falling edge of INT2
(1) Falling edge of INT3
(1)0 0 0 1 0 Both edges of
INT0
(1) Both edges of INT1
(1) Both edges of INT2
(1) Both edges of INT3
(1)0 0 0 1 1 Timer A0 interrupt request
0 0 1 0 0 Timer A1 interrupt request
0 0 1 0 1 Timer A2 interrupt request
0 0 1 1 0 Timer A3 interrupt request
0 0 1 1 1 Timer A4 interrupt request
0 1 0 0 0 Timer B0 interrupt request
0 1 0 0 1 Timer B1 interrupt request
0 1 0 1 0 Timer B2 interrupt request
0 1 0 1 1 Timer B3 interrupt request
0 1 1 0 0 Timer B4 interrupt request
0 1 1 0 1 Timer B5 interrupt request
0 1 1 1 0 UART0 transmit interrupt request
0 1 1 1 1 UART0 receive interrupt request or ACK interrupt request
(2)1 0 0 0 0 UART1 transmit interrupt request
1 0 0 0 1 UART1 receive interrupt request or ACK interrupt request
(2)1 0 0 1 0 UART2 transmit interrupt request
1 0 0 1 1 UART2 receive interrupt request or ACK interrupt request
(2)1 0 1 0 0 Reserved
1 0 1 0 1 Reserved
1 0 1 1 0 Reserved
1 0 1 1 1 Reserved
1 1 0 0 0 A/D0 interrupt request
1 1 0 0 1
Intelligent I/O
interrupt 0 request
Intelligent I/O
interrupt 7 request
Intelligent I/O
interrupt 2 request
Intelligent I/O
interrupt 9 request
1 1 0 1 0
Intelligent I/O
interrupt 1 request
Intelligent I/O
interrupt 8 request
Intelligent I/O
interrupt 3 request
Intelligent I/O
interrupt 10 request
1 1 0 1 1
Intelligent I/O
interrupt 2 request
Intelligent I/O
interrupt 9 request
Intelligent I/O
interrupt 4 request
Intelligent I/O
interrupt 11 request
1 1 1 0 0
Intelligent I/O
interrupt 3 request
Intelligent I/O
interrupt 10 request
Intelligent I/O
interrupt 5 request
Intelligent I/O
interrupt 0 request
1 1 1 0 1
Intelligent I/O
interrupt 4 request
Intelligent I/O
interrupt 11 request
Intelligent I/O
interrupt 6 request
Intelligent I/O
interrupt 1 request
1 1 1 1 0
Intelligent I/O
interrupt 5 request
Intelligent I/O
interrupt 0 request
Intelligent I/O
interrupt 7 request
Intelligent I/O
interrupt 2 request
1 1 1 1 1
Intelligent I/O
interrupt 6 request
Intelligent I/O
interrupt 1 request
Intelligent I/O
interrupt 8 request
Intelligent I/O
interrupt 3 request