
R01UH0218EJ0110 Rev.1.10
Page 109 of 664
Sep 12, 2011
R32C/142 Group and R32C/145 Group
7. Clock Generator
Figure 7.4
CM1 Register
Figure 7.5
CM2 Register
b7 b6 b5 b4
b1
b2
b3
Symbol
CM1
Address
40047h
Reset Value
0010 0000b
b0
Function
Bit Symbol
Bit Name
RW
System Clock Control Register 1 (1)
RW
PLL Oscillator Stop Bit (2, 3)
RW
0: PLL oscillator enabled
1: PLL oscillator disabled
RW
Reserved
Notes:
1. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.
2. When the BCS bit in the CCR register is 0 (PLL clock selected as base clock source), the PLL frequency
synthesizer does not stop oscillating even if the CM10 bit is set to 1.
3. When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM10 bit cannot be changed by a
write access.
Reserved
RW
Reserved
Should be written with 0
Should be written with 1
0 0 1 0 0 0 0
CM10
—
(b4-b1)
—
(b5)
—
(b7-b6)
b7 b6 b5 b4
b1
b2
b3
Symbol
CM2
Address
4004Dh
Reset Value
0000 0000b
b0
Function
Bit Symbol
Bit Name
RW
Oscillator Stop Detection Register (1)
Oscillator Stop Detection
Enable Bit (2, 3)
0: Disable oscillator stop detection
1: Enable oscillator stop detection
RW
Reserved
0: Main clock oscillator has not been
stopped
1: Main clock oscillator stop detected
Oscillator Stop Detection
Flag (4)
RW
Reserved
RO
0: Main clock oscillator active
1: Main clock oscillator stopped
Main Clock Monitor Flag (5)
Notes:
1. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.
2. This bit should be set to 0 when f256 is selected as the base clock source in low speed mode.
3. When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM20 bit cannot be changed by a
write access.
4. When a main clock oscillator stop is detected, this bit becomes 1. It can be set to 0 by a program, however
not to 1. When it is set to 0 while the main clock oscillator is stopped, it does not become 1 until the next
main clock oscillator stop is detected.
5. The main clock state should be determined by several read accesses of this bit after an oscillator stop
detection interrupt is generated.
Should be written with 0
0 0 0 0
0
CM20
—
(b1)
CM22
CM23
—
(b7-b4)