
R01UH0218EJ0110 Rev.1.10
Page 108 of 664
Sep 12, 2011
R32C/142 Group and R32C/145 Group
7. Clock Generator
Figure 7.3
CM0 Register
b7 b6 b5 b4
b1
b2
b3
Symbol
CM0
Address
40046h
Reset Value
0000 1000b
b0
Function
Bit Symbol
Bit Name
RW
System Clock Control Register 0 (1)
RW
0: Peripheral clock source not
stopped in wait mode
1: Peripheral clock source stopped in
wait mode (3)
Peripheral Clock Source
Stop Bit (2)
Clock Output Function
Select Bit
b1 b0
0 0 : I/O port P5_3
0 1 : Output a low speed clock
1 0 : Output f8
1 1 : Output f32
RW
Watchdog Timer Function
Select Bit (7)
XCIN-XCOUT Drive Power
Select Bit (4)
0: Low
1: High
RW
Reserved
0: I/O port
1: XCIN-XCOUT oscillator (5)
Port XC Switch Bit
Main Clock Oscillator (XIN-
XOUT) Stop Bit (2, 6)
0: Main clock oscillator enabled
1: Main clock oscillator disabled
RW
0: Watchdog timer interrupt
1: Reset (8)
Notes:
1. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.
2. When the PM21 bit in the PM2 register is 1 (clock change disabled), bits CM02 and CM05 are not changed
by a write access.
3. fC32 and f2n (whose clock source is the main clock) do not stop.
4. When entering stop mode, the CM03 bit becomes 1.
5. To set the CM04 bit to 1, bits PD8_7 and PD8_6 in the PD8 register should be set to 0 (input), and the
PU25 bit in the PUR2 register should be set to 0 (pull-up resistor disabled).
6. This bit stops the main clock when entering low power mode. It cannot detect whether or not the main clock
oscillator stops. When this bit is set to 1, the clock applied to the XOUT pin becomes high. Since the on-chip
feedback resistor remains connected, the XIN pin is connected to the XOUT pin via the feedback resistor.
7. Set this bit before activating the watchdog timer. When rewriting this bit while the watchdog timer is running,
set it immediately after writing to the WDTS register.
8. Once this bit is set to 1, it cannot be set to 0 by a program.
Should be written with 0
CM02
CM00
CM01
CM03
CM04
CM05
CM06
0
—
(b7)