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Rev. 1.00 Sep. 13, 2007 Page xxii of xxviii
16.10 Usage Notes ...................................................................................................................... 727
16.10.1
Module Stop State Setting ................................................................................ 727
16.10.2
Break Detection and Processing ....................................................................... 727
16.10.3
Mark State and Break Detection ....................................................................... 727
16.10.4
Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only) ..................................................................... 727
16.10.5
Relation between Writing to TDR and TDRE Flag .......................................... 728
16.10.6
Restrictions on Using DTC or DMAC.............................................................. 728
16.10.7
SCI Operations during Power-Down State ....................................................... 729
16.11 CRC Operation Circuit ..................................................................................................... 732
16.11.1
Features............................................................................................................. 732
16.11.2
Register Descriptions........................................................................................ 733
16.11.3
CRC Operation Circuit Operation .................................................................... 735
16.11.4
Note on CRC Operation Circuit........................................................................ 738
Section 17 I
2C Bus Interface 2 (IIC2)..................................................................739
17.1
Features............................................................................................................................. 739
17.2
Input/Output Pins.............................................................................................................. 741
17.3
Register Descriptions........................................................................................................ 742
17.3.1
I
2C Bus Control Register A (ICCRA) ............................................................... 744
17.3.2
I
2C Bus Control Register B (ICCRB) ............................................................... 745
17.3.3
I
2C Bus Mode Register (ICMR)........................................................................ 747
17.3.4
I
2C Bus Interrupt Enable Register (ICIER)....................................................... 748
17.3.5
I
2C Bus Status Register (ICSR)......................................................................... 751
17.3.6
Slave Address Register (SAR).......................................................................... 754
17.3.7
I
2C Bus Transmit Data Register (ICDRT) ........................................................ 755
17.3.8
I
2C Bus Receive Data Register (ICDRR).......................................................... 755
17.3.9
I
2C Bus Shift Register (ICDRS)........................................................................ 755
17.4
Operation .......................................................................................................................... 756
17.4.1
I
2C Bus Format.................................................................................................. 756
17.4.2
Master Transmit Operation ............................................................................... 757
17.4.3
Master Receive Operation ................................................................................ 759
17.4.4
Slave Transmit Operation ................................................................................. 761
17.4.5
Slave Receive Operation................................................................................... 764
17.4.6
Noise Canceller................................................................................................. 765
17.4.7
Example of Use................................................................................................. 766
17.5
Interrupt Request .............................................................................................................. 770
17.6
Bit Synchronous Circuit.................................................................................................... 770
17.7
Usage Notes ...................................................................................................................... 771