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Rev. 1.00 Sep. 13, 2007 Page xvi of xxviii
10.5.3
Transfer Information Writeback Skip Function................................................ 363
10.5.4
Normal Transfer Mode ..................................................................................... 363
10.5.5
Repeat Transfer Mode ...................................................................................... 364
10.5.6
Block Transfer Mode ........................................................................................ 366
10.5.7
Chain Transfer .................................................................................................. 367
10.5.8
Operation Timing.............................................................................................. 368
10.5.9
Number of DTC Execution Cycles ................................................................... 370
10.5.10
DTC Bus Release Timing ................................................................................. 371
10.5.11
DTC Priority Level Control to the CPU ........................................................... 371
10.6
DTC Activation by Interrupt............................................................................................. 372
10.7
Examples of Use of the DTC ............................................................................................ 373
10.7.1
Normal Transfer Mode ..................................................................................... 373
10.7.2
Chain Transfer .................................................................................................. 373
10.7.3
Chain Transfer when Counter = 0..................................................................... 374
10.8
Interrupt Sources...............................................................................................................376
10.9
Usage Notes ...................................................................................................................... 376
10.9.1
Module Stop State Setting ................................................................................ 376
10.9.2
On-Chip RAM .................................................................................................. 376
10.9.3
DMAC Transfer End Interrupt.......................................................................... 376
10.9.4
DTCE Bit Setting.............................................................................................. 376
10.9.5
Chain Transfer .................................................................................................. 377
10.9.6
Transfer Information Start Address, Source Address,
and Destination Address ................................................................................... 377
10.9.7
Transfer Information Modification ................................................................... 377
10.9.8
Endian Format .................................................................................................. 377
Section 11 I/O Ports............................................................................................. 379
11.1
Register Descriptions........................................................................................................ 388
11.1.1
Data Direction Register (PnDDR) (n = 1, 2, 3, 6, A, to F, H to K, and N) ....... 389
11.1.2
Data Register (PnDR) (n = 1, 2, 3, 6, A, to F, H to K, and N) .......................... 390
11.1.3
Port Register (PORTn) (n = 1 to 6, A to F, H to K, and N) .............................. 390
11.1.4
Input Buffer Control Register (PnICR) (n = 1 to 6, A to F, H to K, and N) ..... 391
11.1.5
Pull-Up MOS Control Register (PnPCR) (n = D to F and H to K)................... 392
11.1.6
Open-Drain Control Register (PnODR) (n = 2 and F) ...................................... 393
11.2
Output Buffer Control....................................................................................................... 393
11.2.1
Port 1................................................................................................................. 394
11.2.2
Port 2................................................................................................................. 398
11.2.3
Port 3................................................................................................................. 402
11.2.4
Port 5................................................................................................................. 405
11.2.5
Port 6................................................................................................................. 406