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Rev. 1.00 Sep. 13, 2007 Page xx of xxviii
14.7.2
A/D Converter Activation................................................................................. 620
14.8
Usage Notes ...................................................................................................................... 621
14.8.1
Notes on Setting Cycle ..................................................................................... 621
14.8.2
Conflict between TCNT Write and Counter Clear ........................................... 621
14.8.3
Conflict between TCNT Write and Increment.................................................. 622
14.8.4
Conflict between TCOR Write and Compare Match ........................................ 622
14.8.5
Conflict between Compare Matches A and B................................................... 623
14.8.6
Switching of Internal Clocks and TCNT Operation ......................................... 623
14.8.7
Mode Setting with Cascaded Connection ......................................................... 625
14.8.8
Module Stop State Setting ................................................................................ 625
14.8.9
Interrupts in Module Stop State ........................................................................ 625
Section 15 Watchdog Timer (WDT) ................................................................... 627
15.1
Features............................................................................................................................. 627
15.2
Input/Output Pin ............................................................................................................... 628
15.3
Register Descriptions........................................................................................................ 629
15.3.1
Timer Counter (TCNT)..................................................................................... 629
15.3.2
Timer Control/Status Register (TCSR)............................................................. 629
15.3.3
Reset Control/Status Register (RSTCSR)......................................................... 631
15.4
Operation .......................................................................................................................... 632
15.4.1
Watchdog Timer Mode..................................................................................... 632
15.4.2
Interval Timer Mode......................................................................................... 634
15.5
Interrupt Source ................................................................................................................634
15.6
Usage Notes ...................................................................................................................... 635
15.6.1
Notes on Register Access ................................................................................. 635
15.6.2
Conflict between Timer Counter (TCNT) Write and Increment....................... 636
15.6.3
Changing Values of Bits CKS2 to CKS0.......................................................... 636
15.6.4
Switching between Watchdog Timer Mode and Interval Timer Mode............. 636
15.6.5
Internal Reset in Watchdog Timer Mode.......................................................... 637
15.6.6
System Reset by
WDTOVF Signal................................................................... 637
15.6.7
Transition to Watchdog Timer Mode or Software Standby Mode.................... 637
Section 16 Serial Communications Interface (SCI, IrDA, CRC) ........................ 639
16.1
Features............................................................................................................................. 639
16.2
Input/Output Pins.............................................................................................................. 644
16.3
Register Descriptions........................................................................................................ 645
16.3.1
Receive Shift Register (RSR) ........................................................................... 647
16.3.2
Receive Data Register (RDR)........................................................................... 647
16.3.3
Transmit Data Register (TDR).......................................................................... 648
16.3.4
Transmit Shift Register (TSR) .......................................................................... 648