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Rev. 1.00 Sep. 13, 2007 Page 1100 of 1102
REJ09B0365-0100
TIOR......................486, 1006, 1027, 1045
TMDR ...................484, 1006, 1027, 1045
TSR............................................. 505, 648
TSR (TPU).....................1006, 1027, 1045
TSTR .....................510, 1005, 1027, 1044
TSYR.....................511, 1005, 1027, 1044
VBR...................................................... 39
WTCRA.................165, 1000, 1020, 1039
WTCRB.................165, 1000, 1020, 1039
Repeat transfer mode ...................... 296, 364
Reset ......................................................... 94
Reset state................................................. 68
Resolution............................................... 803
S
Sample-and-hold circuit ......................... 798
Scan mode .............................................. 795
Serial communication interface (SCI) .... 639
Short address mode................................. 353
Single address mode ............................... 292
Single mode............................................ 794
Slave receive mode................................. 764
Slave transmit mode ............................... 761
Sleep instruction exception handling...... 102
Sleep mode ..................................... 942, 964
Slot illegal instructions ........................... 103
Smart card interface................................ 710
Software protection................................. 874
Software standby mode .................. 942, 966
Space state .............................................. 686
Stack status after exception handling...... 104
Standard serial communication interface
specifications for boot mode................... 880
Start bit ................................................... 686
State transition of TAP controller........... 926
State transitions ........................................ 68
Stop bit ................................................... 686
Strobe assert/negate timing..................... 198
Synchronous clearing ............................. 518
Synchronous operation............................ 518
Synchronous presetting........................... 518
System clock (I
φ)............................ 185, 931
T
TAP controller ........................................ 926
Toggle output.......................................... 515
Trace exception handling.......................... 97
Transfer information ............................... 353
Transfer information read
skip function ........................................... 362
Transfer information writeback skip
function ................................................... 363
Transfer modes ....................................... 295
Transmit/receive data.............................. 686
Trap instruction exception handling ....... 101
U
User boot MAT....................................... 822
User boot mode............................... 820, 863
User break controller (UBC)................... 147
User MAT............................................... 822
User program mode ........................ 820, 853
V
Vector table address.................................. 92
Vector table address offset........................ 92
W
Wait control ............................................ 214
Watchdog timer (WDT).......................... 627
Watchdog timer mode............................. 632
Waveform output by compare match...... 514
Write data buffer function....................... 258