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Rev. 1.00 Sep. 13, 2007 Page 1096 of 1102
REJ09B0365-0100
CPU priority control function over DTC
and DMAC ............................................. 140
CRC Operation Circuit ........................... 732
Crystal resonator..................................... 936
Cycle stealing mode................................ 302
D
D/A converter ......................................... 809
Data direction register ............................ 389
Data register............................................ 390
Data transfer controller (DTC) ............... 343
Direct convention ................................... 711
DMA controller (DMAC)....................... 265
Double-buffered structure....................... 686
Download pass/fail result parameter....... 838
DTC vector address ................................ 355
DTC vector address offset ...................... 355
Dual address mode.................................. 291
E
Endian and data alignment ..................... 204
Endian format ......................................... 196
Error protection ...................................... 874
Error signal ............................................. 711
Exception handling................................... 91
Exception-handling state .......................... 68
Extended repeat area............................... 289
Extended repeat area function ................ 304
Extension of chip select (
CS) assertion
period...................................................... 217
External access bus................................. 184
External bus............................................ 189
External bus clock (B
φ) .................. 185, 931
External bus interface ............................. 195
External clock......................................... 937
External interrupts .................................. 123
F
Flash erase block select parameter.......... 847
Flash memory ......................................... 817
Flash multipurpose address area
parameter ................................................ 845
Flash multipurpose data destination
parameter ................................................ 846
Flash pass and fail parameter.................. 839
Flash program/erase frequency
parameter ........................................ 843, 857
Free-running count operation.................. 513
Frequency divider ........................... 931, 938
Full address mode ................................... 353
Full-scale error........................................ 803
G
General illegal instructions ..................... 103
H
Hardware protection ............................... 873
Hardware standby mode ................. 942, 982
I
I/O ports .................................................. 379
I2C bus format......................................... 756
I2C bus interface2 (IIC2)......................... 739
ID code.................................................... 697
Idle cycle................................................. 243
Illegal instruction .................................... 103
Input buffer control register .................... 391
Input capture function............................. 516
Internal interrupts.................................... 124
Internal peripheral bus ............................ 184
Internal system bus ................................. 184
Interrupt .................................................. 100
Interrupt control mode 0 ......................... 131
Interrupt control mode 2 ......................... 133