
Rev. 1.00 Sep. 13, 2007 Page 1095 of 1102
REJ09B0365-0100
Index
Numerics
0 output/1 output..................................... 515
0-output/1-output .................................... 515
16-bit access space.................................. 205
16-bit counter mode................................ 618
16-bit timer pulse unit (TPU) ................. 465
8-bit access space.................................... 204
8-bit timers (TMR) ................................. 593
A
A/D conversion accuracy........................ 803
Absolute accuracy................................... 803
Acknowledge.......................................... 756
Address error ............................................ 98
Address map ............................................. 77
Address modes........................................ 291
Address/data multiplexed
I/O interface.................................... 198, 233
All-module-clock-stop mode .......... 942, 965
Area 0 ..................................................... 199
Area 1 ..................................................... 200
Area 2 ..................................................... 200
Area 3 ..................................................... 201
Area 4 ..................................................... 201
Area 5 ..................................................... 202
Area 6 ..................................................... 203
Area 7 ..................................................... 203
Area division........................................... 192
Asynchronous mode ............................... 686
AT-cut parallel-resonance type............... 936
Available output signal and settings
in each port ............................................. 438
Average transfer rate generator............... 640
B
B
φ clock output control...........................987
Basic bus interface .......................... 197, 207
Big endian ............................................... 196
Bit rate..................................................... 668
Bit synchronous circuit ........................... 770
Block structure........................................ 823
Block transfer mode........................ 297, 366
Boot mode....................................... 820, 849
Boundary scan commands ...................... 915
Buffer operation ...................................... 520
Burst access mode................................... 303
Burst ROM interface....................... 197, 228
Bus access modes.................................... 302
Bus arbitration......................................... 260
Bus configuration.................................... 184
Bus controller (BSC)............................... 159
Bus cycle division ................................... 360
Bus width ................................................ 195
Bus-released state...................................... 68
Byte control SRAM interface ......... 197, 220
C
Cascaded connection............................... 618
Cascaded operation ................................. 524
Chain transfer.......................................... 367
Chip select signals................................... 193
Clock pulse generator ............................. 931
Clock synchronization cycle (Tsy).......... 186
Clocked synchronous mode .................... 703
Communications protocol....................... 882
Compare match A ................................... 616
Compare match B ................................... 617
Compare match count mode ................... 619
Compare match signal............................. 616
Counter operation.................................... 512