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Rev. 1.00 Sep. 13, 2007 Page 1097 of 1102
REJ09B0365-0100
Interrupt controller.................................. 107
Interrupt exception handling sequence ... 135
Interrupt exception handling
vector table ............................................. 125
Interrupt response times.......................... 136
Interrupt sources ..................................... 123
Interrupt sources and vector address
offsets ..................................................... 125
Interval timer .......................................... 634
Interval timer mode................................. 634
Inverse convention.................................. 712
IRQn interrupts ....................................... 123
J
JTAG interface ....................................... 773
L
Little endian............................................ 196
M
Mark state ....................................... 686, 727
Master receive mode............................... 759
Master transmit mode ............................. 757
MCU operating modes.............................. 69
Memory MAT configuration .................. 822
Mode 2...................................................... 75
Mode 4...................................................... 75
Mode 5...................................................... 75
Mode 6...................................................... 76
Mode 7...................................................... 76
Mode pin................................................... 69
Multi-clock mode ................................... 963
Multiprocessor bit................................... 697
Multiprocessor communication
function................................................... 697
N
NMI interrupt.......................................... 123
Noise canceler......................................... 765
Nonlinearity error.................................... 803
Non-overlapping pulse output................. 583
Normal transfer mode ............................. 363
Normal transfer mode ............................. 295
Number of Access Cycles ....................... 197
O
Offset addition ........................................ 307
Offset error.............................................. 803
On-board programming .......................... 849
On-board programming mode................. 817
On-chip baud rate generator.................... 689
On-chip ROM disabled extended mode.... 69
On-chip ROM enabled extended mode..... 69
Open-drain control register ..................... 393
Oscillator................................................. 936
Output buffer control .............................. 393
Output trigger.......................................... 582
Overflow ......................................... 618, 632
P
Parity bit.................................................. 686
Periodic count operation ......................... 513
Peripheral module clock (P
φ).......... 185, 931
Phase counting mode .............................. 531
Pin assignments......................................... 10
Pin functions ............................................. 17
PLL circuit ...................................... 931, 938
Port function controller ........................... 447
Port register............................................. 390
Power-down modes................................. 941
Procedure program.................................. 867
Processing states ....................................... 68
Program execution state............................ 68
Program stop state..................................... 68