參數(shù)資料
型號(hào)： QT0086302TME
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 59/62頁
文件大小： 268K
代理商： QT0086302TME
IRQ Driveback
912-3000-047
Revision: 1.0
Page 49
January 08, 1998
OPTi
Appendix A IRQ Driveback Protocol
The OPTi PCI IRQ Driveback cycle provides a clean and sim-
ple way to convey interrupt and DMA status information to the
host. The protocol is reliable and does not in any way com-
promise PCI compatibility.
1.
Whenever a PCI peripheral device must signal an IRQ or
SMI# to the system, it asserts its REQ# line to the host
for one PCI clock, deasserts it for one PCI clock, then
asserts it again and keeps it low until acknowledged.
2.
The host recognizes this sequence as a high-priority
request and immediately removes all other bus grants
(GNT# lines). Once the previous bus owner is off the
bus, the host acknowledges the high-priority request with
GNT# as usual.
3.
The peripheral device logic runs an I/O write cycle to the
IRQ Driveback address specified in the PCI configura-
tion registers, and releases REQ#.
4.
The host latches the information on AD[31:0] and sets
the IRQ lines appropriately.
5.
An optional second burst data cycle can take place to
convey additional interrupt information.
PCI-type devices on the secondary side of bridge chips can
use this same protocol to convey their interrupt requests
through the bridge to the host. The format of the driveback
cycle request is illustrated in the figure. A second data phase
is also possible.
A.1
The charts below illustrate the interrupt information indicated
IRQ bits indicate whether that IRQ line is being driven high or
low. The EN# bits indicate whether that IRQ is enabled to be
changed or not. When the EN# bit is low, the value on the
IRQ bit is valid. The device containing the central interrupt
controller claims this I/O write cycle, and can then change its
internal IRQ line state to match the value sent.
Driveback Cycle Format
When a PCI device needs to generate an interrupt to the sys-
tem, it runs a driveback cycle with the Enable bit low for each
IRQ line under its control. For example, a device on PCI
could run a driveback cycle with IRQ3 high and EN3# low to
generate IRQ3 to the system. When the interrupt has been
serviced and the device deasserts its interrupt, it starts
another driveback cycle with IRQ3 low and EN3# low.
During both of these instances, if the device controls inter-
rupts other than IRQ3, it must set its EN# bits low for
all
channels it controls, not just for the interrupt whose state has
changed. The other IRQs must be driven with their previously
used values.
Figure A-1
IRQ Driveback Cycle High-Priority Request
Table A-1
Information Provided on a Driveback Cycle
PCICLK
REQ#
GNT#
AD[31:0]
//
//
//
//
Low
Word
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10
IRQ9
IRQ8
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
High
Word
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
EN15# EN14# EN13# EN12# EN11# EN10# EN9#
EN8#
EN7#
EN6#
EN5#
EN4#
EN3#
EN2#
EN1#
EN0#
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