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參數(shù)資料
| 型號： | QT0086302TME |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 18/62頁 |
| 文件大小： | 268K |
| 代理商： | QT0086302TME |
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82C814
Page 8
January 08, 1998
912-3000-047
Revision: 1.0
OPTi
CRST#
77
O
Reset:
Used to reset the docking station PCI bus. This signal defaults to
“asserted” until specifically programmed to go high.
CC/BE[3:0]#
65, 56, 41,
29
I/O
Bus Command and Byte Enables 3 through 0:
These pins are the multi-
plexed PCI command and byte enable lines. Normally outputs, these pins are
inputs during master cycles.
CPAR
43
I/O
Parity:
This signal is an input either during PCI slave cycles for address and
write data phases or during PCI master cycle for read data phase; otherwise it is
an output.
CCLK[3:0]
74, 53, 34,
19
O
Clock 3 through 0:
These pins generate individual clocks to each PCI device
on the dock.
CFRAME#
55
I/O
Cycle Frame:
The 82C814 drives this signal to indicate the beginning and dura-
tion of an access.
CIRDY#
51
I/O
Initiator Ready:
The 82C814 drives this signal to indicate its ability to complete
the current data phase of the transaction.
CTRDY#
50
I/O
Target Ready:
The 82C814 monitors this input from the slot interface slave
device to determine when it can complete the cycle. PCI devices on the slots
return CTRDY# to the 82C814 which in turn drives host TRDY#.
CSTOP#
48
I/O
Stop:
This signal is used by the target to request the master to stop the current
transaction. The 82C814 will back-off the current cycle and retry it later.
CBLOCK#
47
I/O
Bus Lock:
The 82C814 uses this signal to indicate an atomic operation that
may require multiple transactions to complete.
CDEVSEL#
49
I/O
Device Select:
This signal is normally an input from the slot interface device
claiming the cycle. The 82C814 claims the cycle ahead of time on the host side.
CPERR#
46
I/O
Parity Error:
All slot interface devices use this signal to report data parity
errors, during any PCI transaction except a Special Cycle.
CSERR#
45
I/O
System Error:
All slot interface devices use this signal to report address parity
errors, data parity errors on the Special Cycle command, or any other system
error where the result will be catastrophic.
CEXT_GNT#
84
I
External Arbiter Grant Input:
This signal is asserted by an external arbiter to
grant the secondary PCI bus to the 82C814. When using an external arbiter
CREQ[2:0]# and CGNT[2:0]# are not functional and should be pulled high.
CREQ3#
I
Bus Master Request Line 3:
Request/grant signal pairs are provided to
accommodate up to four PCI bus masters on the docking station.
CREQ[2:0]#
82, 80, 78
I
Bus Master Request Lines 2 through 0:
Request/grant signal pairs are pro-
vided to accommodate up to four PCI bus masters on the docking station.
CEXT_REQ#
85
O
External Arbiter Request Output:
The 82C814 asserts this signal to request
the secondary PCI bus from an external arbiter. When using an external arbiter
CREQ[2:0]# and CGNT[2:0]# are not functional and should be pulled high.
CGNT3#
O
Bus Grant Line 3:
Request/grant signal pairs are provided to accommodate up
to four PCI bus masters on the docking station.
CGNT[2:0]#
83, 81, 79
O
Bus Grant Lines 2 through 0:
Request/grant signal pairs are provided to
accommodate up to four PCI bus masters on the docking station.
3.2.3
PCI Docking Interface Pins (cont.)
Signal Name
Pin
No.
Signal
Type
Signal Description
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