參數(shù)資料
型號(hào)： QT0086302TME
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 16/62頁(yè)
文件大小： 268K
代理商： QT0086302TME
82C814
Page 6
January 08, 1998
912-3000-047
Revision: 1.0
OPTi
3.2
Signal Descriptions
3.2.1
Host Interface PCI Signals
Signal Name
Pin
No.
Signal
Type
Signal Description
AD[31:0]
99, 100,
102:107,
111:115,
117:119,
134, 135,
137:142,
1:6, 8, 9
I/O
Address and Data Lines 31 through 0:
This bus carries the address during the
address phase and the data during the data phase of a PCI cycle. During the
address phase these pins are inputs only and during the data phase they are
I/Os.
C/BE[3:0]#
108,
120,
133, 143
I/O
Bus Command and Byte Enables 3 through 0:
These inputs provide the com-
mand type information during the address phase and carry the byte enable infor-
mation during the data phase.
PAR
132
I/O
Parity:
This bit carries parity information for both the address and data phases of
PCI cycles. During the address or data write phase of a PCI cycle this pin is an
input only. During the data read phase it acts as an output only.
PCICLK
125
I
PCI Clock:
Provides timing for all transactions on the host PCI bus; normally
33MHz. This same clock can be used for timing the slot interfaces, or can be
divided. The slot interfaces can also run from the alternative EXTCLK input.
VENID#
13
O
Drive Vendor ID:
This pin can be used to enable an external tristate buffer to
drive vendor ID bits onto the PCI bus. This feature allows system card designers
to drive a unique PCI card ID for identification by software.
EXTCLK
I
External Clock:
Provides alternative clock source for transactions on the slot
interface PCI bus. The frequency can be any value but is usually 20MHz or
25MHz. It should be tied low if not used. This pin is automatically sensed just after
reset time to determine whether an external clock frequency is being applied. If
not, the function defaults to VENID#.
INTC#
I/O
See Section 3.2.4 for interrupt information.
CLKRUN#
10
I/O
Clock Run:
Pulled low by any device needing to use the PCI bus. If no devices
pull this pin low, the host PCI bus controller is allowed to stop the PCICLK signal.
The interrupt logic of the 82C814 uses this signal to request a restart of PCICLK
in order to send an interrupt request.
IRQLATCH
11
I/O
Interrupt Latch:
For use on chipsets without IRQ driveback capability, the
82C814 logic can drive this line low to drive ISA IRQ lines using an external latch.
This pin is also a strap option, refer to Section 5.3
INTA#
I/O
See Section 3.2.4 for interrupt information.
FRAME#
121
I/O
Cycle Frame:
Driven by PCI bus masters to indicate the beginning and duration
of an access.
IRDY#
122
I/O
Initiator Ready:
Asserted by the PCI bus master to indicate that it is ready to
complete the current data phase of the transaction.
TRDY#
123
I/O
Target Ready:
Asserted by the PCI bus target (when the 82C814 is a slave) to
indicate that it is ready to complete the current data phase of the transaction. PCI-
type devices on the slot interfaces return CTRDY# to the 82C814, which in turn
drives TRDY# to the host. The 82C814 logic drives TRDY# directly for 82C814
configuration register accesses.
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