
82C814
912-3000-047
Revision: 1.0
Page 25
January 08, 1998
OPTi
PCICFG 16h
PCI Secondary Bus Status Register - Byte 0
Default = 00h
Fast back-to-
back capability 
on docking 
interface PCI 
bus (RO):
0 = No (always)
Reserved (RO)
PCICFG 17h
PCI Secondary Bus Status Register - Byte 1
Default = 02h
Parity error 
on docking 
interface 
PCI bus:
0 = No
1 = Yes
Write 1 to clear
Received 
system error on 
docking inter-
face PCI bus:
0 = No
1 = Yes
Write 1 to clear
Received mas-
ter abort on 
docking inter-
face PCI bus 
(RO):
0 = No
1 = Yes
Received 
target abort on 
docking inter-
face PCI bus 
(RO):
0 = No
1 = Yes
Signalled 
target abort on 
docking inter-
face PCI bus:
0 = No
1 = Yes
Write 1 to clear
DEVSEL# timing on docking inter-
face PCI bus (RO):
00 = Fast
01 =Medium (always)
10 = Slow
11 = Reserved
PERR# active 
as master on 
docking inter-
face PCI bus 
(RO):
0 = No
1 = Yes
PCICFG 18h
-
Indicates the number of the PCI bus to which the host interface of the 82C814 chip is connected. 
-
Defaults to 0. 
-
The logic uses this value to determine whether Type 1 configuration transactions on the docking interface should be converted to Spe-
cial Cycle transactions on the host interface.
Primary PCI Bus Number Register
Default = 00h
PCICFG 19h
-
Indicates the number of the PCI bus to which the docking interface of the 82C814 chip is connected. 
-
Defaults to 0. 
-
The logic uses this value to determine whether Type 1 configuration transactions on the host interface should be converted to Type 0 
transactions on the docking interface.
Secondary PCI Bus Number Register
Default = 00h
PCICFG 1Ah
-
Indicates the number of the highest-numbered PCI bus on the docking interface side. 
-
The 82C814 logic uses this value in conjunction with the Secondary Bus Number to determine when to respond to Type 1 configuration 
transactions on the host interface and pass them onto the docking interface. 
-
Defaults to 0.
Subordinate Bus Number Register
Default = 00h
PCICFG 1Bh
Latency Timer Register
Default = 00h
Indicates the time-out value for the docking interface.
PCICFG 1Ch
Memory Window 0 Base Address Bits:
-
The 32-bit Memory Window 0 Base Address Register selects the start address of one of two possible CardBus memory windows to the 
slot interface. 
-
Bits [11:0] are read-only and are always 0. 
-
The memory windows are globally enabled by bit 04h[1] (Command Register). 
-
Prefetching is enabled by bit 3Fh[0] (Bridge Control Register) and defaults to "enabled." 
-
The Limit address can be set below the Base address to individually disable a window.
Memory Window 0 Base Address Register - Byte 0: Address Bits [7:0]
Default = 00h
PCICFG 1Dh
Memory Window 0 Base Address Register - Byte 1: Address Bits [15:8]
Default = F0h
PCICFG 1Eh
Memory Window 0 Base Address Register - Byte 2: Address Bits [23:16]
Default = FFh
PCICFG 1Fh
Memory Window 0 Base Address Register - Byte 3: Address Bits [31:24]
Default = FFh
Table 5-1
Base Register Group - PCICFG 00h-4Fh (cont.)
7
6
5
4
3
2
1
0