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參數(shù)資料
| 型號： | QT0086302TME |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 25/62頁 |
| 文件大小： | 268K |
| 代理商： | QT0086302TME |
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82C814
912-3000-047
Revision: 1.0
Page 15
January 08, 1998
OPTi
4.5
The host interfaces to the 82C814 chip through the primary
PCI bus. This bus operates according to PCI standards,
including the later addition of the CLKRUN# signal. CLK-
RUN# is normally controlled by the host, but at certain times
can be driven low by the 82C814 chip when the chip is
requesting that PCICLK be restarted or sped up. Refer to the
PCI Mobile Design Guide for the requirements of CLKRUN#.
Primary PCI Bus
CLKRUN# is controlled by PCICFG 50h[2].
4.6
The PCI-to-CardBus bridge circuit of the 82C814 chip recog-
nizes the cycle being performed by the current system bus
master and responds as required.
PCI-to-CardBus Bridge
4.6.1
If the access is a configuration cycle, the PCI bridge simply
accesses the local PCI Configuration Register set directly.
The PCI cycle controller claims all configuration accesses to
PCI Function 0 of the 82C814 chip.
Configuration Cycle
4.6.1.1
Translation Between Type 0 and Type 1
Configuration Cycles
The 82C814 logic converts Type 1 configuration cycles on
the host PCI bus to Type 1, Type 0, or a Special Cycle as is
typically required of a PCI-to-PCI bridge. However, in a PCI-
to-PCI bridge, Type 1 configuration cycles on the secondary
PCI bus can be converted only to Type 1 or Special Cycles
on the primary bus, never to Type 0.
The 82C814 logic is different from the standard PCI-to-PCI
bridge in this regard. The 82C814 allows the secondary to act
as a primary. PCICFG 52h[0] is used to enable this feature.
With this feature selected, master devices on the docking sta-
tion interface can program the PCI configuration registers of
the 82C814 (and any other PCI device on the host PCI bus).
To do so, the secondary bus master must generate a Type 1
configuration cycle. The 82C814 logic will pass this to the pri-
mary as a Type 0 configuration cycle. Since the 82C814 PCI
configuration registers sit on the primary, they are also acces-
sible this way. Thus, on the primary the 82C814 acts as both
initiator by generating the configuration cycle, and as target
by claiming the cycle it just generated.
Note that secondary bus masters can access PCI configura-
tion registers on any primary bus device, not just the 82C814.
Table 4-2
CLKRUN# Control Bits
Table 4-3
Translation Feature Configuration Bit
7
6
5
4
3
2
1
0
PCICFG 50h
PCI Host Feature Control Register
Default = 01h
CLKRUN# (on
host interface):
0 = Enabled
per PCI
1 = Disabled,
CLKRUN#
tristated
7
6
5
4
3
2
1
0
PCICFG 52h
Docking Feature Control Register 2
Default = 0Fh
Type 1 to Type
0 conversion
blocked from
secondary to
primary:
0 = No
1 = Yes
(Default)
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