參數(shù)資料
型號: QT0086302TME
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 49/62頁
文件大?。?/td> 268K
代理商: QT0086302TME
82C814
912-3000-047
Revision: 1.0
Page 39
January 08, 1998
OPTi
Window 1 Mask Bits:
-
Mask register bits [23:2] allow Window 0 to be aliased throughout the memory or I/O address space.
-
Setting any bit to a 1 masks out the comparison on this bit.
-
The register should be written to 0 to decode the entire address.
-
Bits [1:0] are always 11 (masked).
RO:
Always returns 1.
PCICFG 99h
Window 1 Mask Register - Byte 1: Mask Bits [15:8]
Default = 00h
PCICFG 9Ah
Window 1 Mask Register - Byte 2: Mask Bits [23:16]
Default = 00h
PCICFG 9Bh
Window 1 Control Register
Default = 48h
Window points
to ISA bus:
0 = No
1 = Yes
Reads are
prefetchable:
0 = No
1 = Yes
Set to 0 for I/O
window
Writes can be
posted:
0 = No
1 = Yes
Set to 0 for I/O
window
Reserved
Cycle
qualifier:
0 = I/O
1 = Memory
(Default)
Window 1
Trap/SMI#:
0 = Disable
1 = Enable
Reserved
PCICFG 9Ch-9Fh
Reserved
Default = 00h
PCICFG A0h
Window 2 Start Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Window 2 Address Bits:
-
Register bits [31:0] indicate the start address for Window 2.
-
The selection between memory or I/O, as well as other feature selections, are made through the
Window 2 Control Register.
RO:
Always returns
0
If memory:
reads 0.
If I/O: Decoding
0 = 16-bit
AD[31:16] = 0
1 = 32-bit
PCICFG A1h
Window 2 Start Address Register - Byte 1: Address Bits [15:8]
Default = FFh
PCICFG A2h
Window 2 Start Address Register - Byte 2: Address Bits [23:16]
Default = FFh
PCICFG A3h
Window 2 Start Address Register - Byte 3: Address Bits [31:24]
Default = FFh
PCICFG A4h
Window 2 Stop Address Register - Byte 0: Address Bits [7:0]
Default = 00h
Window 2 Stop Address Bits:
-
Register bits [31:0] indicate the stop address for one of the eight memory or I/O windows.
RO:
Always returns 0
PCICFG A5h
Window 2 Stop Address Register - Byte 1: Address Bits [15:8]
Default = 00h
PCICFG A6h
Window 2 Stop Address Register - Byte 2: Address Bits [23:16]
Default = 00h
PCICFG A7h
Window 2 Stop Address Register - Byte 3: Address bits [31:24]
Default = 00h
PCICFG A8h
Window 2 Mask Register - Byte 0: Mask Bits [7:0]
Default = 03h
Window 2 Mask Bits:
-
Mask register bits [23:2] allow Window 0 to be aliased throughout the memory or I/O address space.
-
Setting any bit to a 1 masks out the comparison on this bit.
-
The register should be written to 0 to decode the entire address.
-
Bits [1:0] are always 11 (masked).
RO:
Always returns 1.
PCICFG A9h
Window 2 Mask Register - Byte 1: Mask Bits [15:8]
Default = 00h
PCICFG AAh
Window 2 Mask Register - Byte 2: Mask Bits [23:16]
Default = 00h
Table 5-6
Docking Station Window Registers - PCICFG 80h-EFh (cont.)
7
6
5
4
3
2
1
0
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