參數(shù)資料
型號(hào)： QT0086302TME
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 30/62頁(yè)
文件大?。?/td> 268K
代理商： QT0086302TME
82C814
Page 20
January 08, 1998
912-3000-047
Revision: 1.0
OPTi
4.8.5
The 82C814 logic provides register settings PCICFG 52h[7:4]
to compensate for trace delays. Some compensation is gen-
PCI Clock Buffering
erally required. Table 4-6 highlights the register used for com-
pensating trace delays.
Table 4-6
Register used to Delay Internal PCICLK to Compensate for Trace Delays
4.9
The 82C814 supports a total of three interrupt schemes from
the secondary PCI bus.
Interrupt Support
1.
PCI
interrupts INTA#, INTB#, INTC#, and INTD# can be
mapped internally to system PCIRQ[3:0]# lines.
2.
PCI IRQ driveback
cycles can generate any ISA inter-
rupt. The OPTi PCI-ISA Bridge uses this scheme to gen-
erate interrupts in a parallel format back to the host
controller via the 82C814 chip.
3. The
Compaq Serial IRQ
scheme uses a single wire,
IRQSER, along with the PCICLK to transmit interrupts in
a serial format.
The available schemes are described below.
4.9.1
The PCI INTA#, INTB#, INTC#, and INTD# lines can be
mapped to any of the primary side PCIRQ[3:0]# lines.
PCICFG 48-4Ch provide controls for this mapping.
PCI INTx# Implementation
4.9.2
A detailed overview of the IRQ driveback cycle is provided in
Appendix A. The logic used to implement this mechanism is
relatively simple. The trigger events for a driveback cycle are
any transition on an interrupt line, or an SMI event as enabled
by the 82C814 configuration registers. The request goes to
the Request Arbiter logic, which always gives the driveback
cycle top priority. Once the REQ# pin is available, the
Request Arbiter asserts REQ# on behalf of the IRQ Drive-
back logic and toggles REQ# according to the driveback pro-
tocol discussed in Appendix A.
IRQ Driveback Logic
Once the host PCI controller returns GNT#, the driveback
logic writes to the IRQ driveback address location specified in
the PCI configuration registers as shown in Appendix A.
7
6
5
4
3
2
1
0
PCICFG 52h
Docking Feature Control Register 2
Default = 0Fh
Secondary PCICLK Skew:
This value selects the approximate delay, in nanoseconds, that the
internal secondary PCICLK must be skewed in order to compensate
for external buffer delays.
0000 = No delay
0001 = 1ns
.....
1101 = 13ns
1110 = 14ns
0010 = 2ns
1111 = 15ns
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