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參數(shù)資料
| 型號(hào)： | PowerPC 440 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC PowerPC Embedded Processor Cores(32位 RISC PowerPC 嵌入式處理器) |
| 中文描述： | 32位RISC PowerPC嵌入式處理器內(nèi)核（RISC的32位的PowerPC嵌入式處理器） |
| 文件頁(yè)數(shù)： | 9/18頁(yè) |
| 文件大?。?/td> | 317K |
| 代理商： | POWERPC 440 |
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PowerPC 440 Core
09/21/1999
Page 9 of 18
store hits; every store operation generates a PLB write request. (Although write-through requests to non-
cacheable memory can be gathered as previously mentioned).
D-Cache Store Allocation
The D-Cache can be programmed whether or not to allocate a line on a D-Cache store miss. Write-on-
allocate is enabled by default. In this mode, a store miss to cacheable memory forces the data cache
controller to allocate a line in the data cache and generate a line fill. In contrast, when “without allocate”
is enabled, a store miss to cacheable memory will
not
allocate a line data cache and will simply write the
data to memory.
Big Endian and Little Endian Support
The PPC440 supports big endian or little endian byte ordering for instructions and data stored in external
memory. The PowerPC Book E architecture is endian neutral; each page in memory can be configured for
big or little endian byte ordering via a storage attribute contained in the TLB entry for that region.
Strapping signals on the PPC440 core initialize the beginning TLB entry’s endian attribute, so the
PPC440 can boot from little or big endian memory.
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