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參數(shù)資料
| 型號(hào)： | PowerPC EM603e |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-Bit PowerPC Reduced Instruction Set Computer (RISC) Microprocessor(32-位 PowerPC 精簡(jiǎn)指令集微處理器) |
| 中文描述： | 32位PowerPC精簡(jiǎn)指令集計(jì)算機(jī)（RISC）微處理器（32 -位PowerPC的精簡(jiǎn)指令集微處理器） |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 64K |
| 代理商： | POWERPC EM603E |
PowerPC EM603e and 603e
Microprocessors optimized for embedded applications
Highlights
PowerPC EM603e
*
and 603e family
processors are 32-bit implementations
of the PowerPC Reduced Instruction Set
Computer (RISC) microprocessor family.
They offer high clock frequency and
efficient throughput driven by five
execution units and the ability to issue
and retire two instructions per clock.
Although all models provide industry-
leading value because of a low-cost
manufacturing process, EM603e models
can provide even greater value in
applications which do not need floating-
point functionality
All PowerPC EM603e and 603e proces-
sors are price-positioned and function-
ally optimized for the high-end embed-
ded market, making them ideal for
networking and communications
applications.
Summary of Features:
Power Management Unit
Low-power design
Dynamic power management
Doze, nap, and sleep power savings
modes
3.3V or 2.5V core power supply
available
Instruction Fetching &
Branch Unit
6-instruction prefetch queue
Static branch prediction
Dispatch Unit
Dispatches 2 instructions per cycle
4-stage pipeline: Fetch, Dispatch,
Execute, and Complete
Load/Store Unit
One cycle cache access
Executes cache and TLB instructions
Alignment and number
denormalization
Hit under reload instruction
Fixed-Point Execution Unit
One cycle add, subtract, shift, or rotate
Hardware multiply and divide
Thirty-two, 32-bit General Purpose
Registers
Floating-Point Execution Unit
(PowerPC 603e only)
Optimized for single-precision
multiply/add
IEEE-754 standard single-and double-
precision floating point arithmetic
Thirty-two, 64-bit Floating Point
Registers
System Unit
Executes condition register logical,
special register transfer, and other
system instructions
Executes integer add/compare
instructions
Memory Management Unit
52-bit virtual and 32-bit real addressing
8 Block Address Translation registers
64-entry, 2-way data and
instruction TLB
Fast-trap mechanism for software
reload TLB
Cache Unit
16K, 4-way set associative
instruction cache
16K, 4-way set associative data cache
3-state hardware coherency (MEI);
compatible with four-state MESI
protocol
Physically tagged and addressed
Copy-back data cache
Hardware support for data coherency
Bus Interface Unit
General purpose interface for a wide
range of system configurations
32-bit address and selectable 64- or
32-bit data bus
Powerful diagnostic and test interface
through the Common On-Chip Proces-
sor (COP) and IEEE 1149.1 (JTAG)
interface
Parity checking on bus
Fast reset due to Level Sensitive
Scan Design (LSSD)
Bi-Endian operation
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