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參數(shù)資料
| 型號： | PowerPC 440 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC PowerPC Embedded Processor Cores(32位 RISC PowerPC 嵌入式處理器) |
| 中文描述： | 32位RISC PowerPC嵌入式處理器內(nèi)核（RISC的32位的PowerPC嵌入式處理器） |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 317K |
| 代理商： | POWERPC 440 |
PowerPC 440 Core
09/21/1999
Page 15 of 18
Power Management
The PPC440 core, in keeping with the IBM PowerPC 400 family tradition, utilizes aggressive power
management techniques for minimizing power. The PPC440 utilizes three key techniques: redundant
operand registers, half-cycle latch stabilization, and dynamic clock gating.
Redundant Operand Registers
Redundant operand registers are used at various pipeline stages for feeding operands to each of the
execution units. This saves power by preventing unused units from seeing the operand values being used
by other units and improves performance by reducing loading and wire length in critical stages.
Half-Cycle Latch Stabilization
Half-cycle stabilization latches minimize the propagation of glitches to downstream logic. This is easily
employed since the PPC440 core contains a master/slave latch arrangement for scan-test purposes.
Therefore, a master-only latch is simply needed in the logic path that is switching in the first half of a
cycle. For example, if the select lines for a mux are being determined in the first half of a cycle, then by
putting a master-only latch on these select lines before delivering them to the mux, the mux outputs are
prevented from glitching while the select lines are being determined. Conversely, if the data lines are
unstable in the first half of a cycle, a stabilization latch may be used on the data inputs, while leaving the
select lines alone.
Dynamic Clock Gating
The most important feature of the PPC440’s dynamic power management is the extensive use of clock
gating. Given the PPC440’s master/slave latch organization, there are two possible gates that can be used.
The relationship between them, and their relative affect on the clock splitter and hence power are shown
in Figure 5.
Figure 5 - PPC440 Clock Gating
In this figure, the early gate blocks the phase 1 clock and prevents the master latch from loading, while
the late gate blocks the phase 2 clock and prevents the slave latch from loading. As illustrated in the
simplified block diagram of the clock splitter, the early gate must arrive by mid-cycle -- which is when the
system clock falls. If the gate is activated by this point, then the net effect is that internal to the clock
splitter the fall on the system clock is never observed, and both the phase 1 and the phase 2 clock splitter
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