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參數(shù)資料
| 型號(hào)： | PowerPC 440 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC PowerPC Embedded Processor Cores(32位 RISC PowerPC 嵌入式處理器) |
| 中文描述： | 32位RISC PowerPC嵌入式處理器內(nèi)核（RISC的32位的PowerPC嵌入式處理器） |
| 文件頁(yè)數(shù)： | 11/18頁(yè) |
| 文件大?。?/td> | 317K |
| 代理商： | POWERPC 440 |
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PowerPC 440 Core
09/21/1999
Page 11 of 18
Interrupt Handling Logic
The PPC440 services exceptions generated by error conditions, the internal timer facilities, debug events,
and the external interrupt controller (EIC) interface. Altogether, there are sixteen different interrupt types
supported.
Interrupts are divided into two classes, critical and non-critical. Each class of interrupt has its own pair of
save/restore registers for holding the program counter and machine state. Separate save/restore registers
allow the PPC440 to quickly handle critical interrupts even within a non-critical interrupt handler.
When an interrupt is taken, the PPC440 automatically writes the program counter and machine state to
save/restore register SRR0 and SRR1 respectively for non-critical interrupts, or CSRR0 and CSRR1
respectively for critical interrupts. The machine status and program counter are automatically restored at
the end of an exception handler when the return from interrupt (rfi) or return from critical interrupt (rfci)
instruction is executed.
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