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參數(shù)資料
| 型號： | PowerPC 440 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC PowerPC Embedded Processor Cores(32位 RISC PowerPC 嵌入式處理器) |
| 中文描述： | 32位RISC PowerPC嵌入式處理器內核（RISC的32位的PowerPC嵌入式處理器） |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 317K |
| 代理商： | POWERPC 440 |
PowerPC 440 Core
09/21/1999
Page 13 of 18
Debug Logic
All architected resources on the PPC440 can be accessed through the debug logic. Upon a debug event,
the PPC440 provides debug information to an external debug tool. Three different types of tools are
supported depending on the debug mode: ROM Monitors, JTAG debuggers and instruction trace tools.
Internal Debug Mode
In internal debug mode, a debug event enables exception-handling software at a dedicated interrupt vector
to take over the PPC440 and communicate with a debug tool. Exception-handling software has read-write
access to all registers and can set hardware or software breakpoints. ROM monitors typically use the
internal debug mode.
External Debug Mode
In external debug mode, the PPC440 enters stop state (i.e., stops instruction execution) when a debug
event occurs. This mode offers a debug tool non-invasive read-write access to all registers in the PPC440
via the JTAG interface. Once the PPC440 is in stop state, the debug tool can start the PPC440, step an
instruction, freeze the timers or set hardware or software break points. In addition to PPC440 control, the
debug logic is capable of writing instructions into the instruction cache, eliminating the need for external
memory during initial board bring up.
Debug Wait Mode
Debug wait mode offers the same functionality as external debug mode with one difference; in debug wait
mode, the PPC440 will respond to interrupts and temporarily leave stop state to service them before
returning to debug wait mode. In external debug mode, by contrast, interrupts are disabled while in stop
state. Debug wait mode is particularly useful when debugging real-time control systems.
Real-Time Trace Debug Mode
In real-time trace debug mode, instruction trace information is continuously broadcast to the trace port.
When a debug event occurs, an external debug tool saves instruction trace information before and after the
event. The number of traced instructions depends only on the memory buffer depth of the trace tool.
Debug Events
Debug events signal the debug logic to either stop the PPC440, put the PPC440 in debug wait state, cause
a debug exception, or save instruction trace information, depending on the debug mode. Table 4 on the
following page lists the possible debug events and their description.
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