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參數(shù)資料
| 型號(hào)： | PowerPC 440 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC PowerPC Embedded Processor Cores(32位 RISC PowerPC 嵌入式處理器) |
| 中文描述： | 32位RISC PowerPC嵌入式處理器內(nèi)核（RISC的32位的PowerPC嵌入式處理器） |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 317K |
| 代理商： | POWERPC 440 |
PowerPC 440 Core
09/21/1999
Page 17 of 18
Core External Interfaces
Processor Local Bus (PLB) interface
The PPC440 accesses system resources through three independent PLB interfaces: one for instruction
fetches, one for data reads, and a third for data writes. Each PLB controller is a 128-bit PLB master. The
PLB is the high performance CoreConnect bus optimized for SOC design.
DCR Bus interface
The Device Control Register (DCR) bus is a configuration bus for components external to the PPC440.
Using the DCR bus to manage status and configuration registers reduces PLB traffic and improves system
bandwidth and integrity. System resources on the DCR Bus are protected or isolated from wayward code
since the DCR bus is not part of the system memory map.
Auxiliary Processor Unit (APU) Interface
The APU interface enables a custom design implementation to tightly couple coprocessor-type macros to
the PPC440.
The APU interface provides sufficient functionality to attach macros such as a full PowerPC Floating
Point Unit (single or double precision), a multimedia macro, DSP, or other custom functions
implementing algorithms appropriate for the system application. The APU interface supports dual-issue
pipeline designs, and utilizes a full 128-bit load/store path to the D-Cache. The interface can be used with
macros that contain their own register files, or with simpler macros which use the CPU’s register file for
source and/or target operands.
The APU interface provides customers the capability to execute instructions that are not part of the
PowerPC Book E architecture concurrently with the PPC440. Accordingly, areas have been reserved
within the architected instruction space to allow for customer- or application-specific extensions.
External Interrupt Controller (EIC) Interface
The EIC interface extends interrupt support to logic external to the PPC440 through the external and
critical interrupt signals. These inputs are level sensitive. The critical interrupt and external interrupt
signals are conceptually logic OR’s of all implementation-specific critical and non-critical interrupts
outside the core.
Debug interface
Debugging interfaces on the PPC440, consisting of the JTAG and instruction trace ports, offer access to
resources internal to the core and assist in software development. The JTAG port provides the ability for
external debug tools to gain control of the processor for debug purposes. This interface provides
debuggers such as RISCWatch with processor control that includes stepping, stopping, and starting the
PPC440. The Trace port furnishes programmers with a mechanism for acquiring instruction traces. This
trace information is captured via an external trace tool, such as RISCTrace. The PPC440 is capable of
tracing before, around, or after an occurring debug event.
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