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參數(shù)資料
| 型號(hào)： | PowerPC 440 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC PowerPC Embedded Processor Cores(32位 RISC PowerPC 嵌入式處理器) |
| 中文描述： | 32位RISC PowerPC嵌入式處理器內(nèi)核（RISC的32位的PowerPC嵌入式處理器） |
| 文件頁(yè)數(shù)： | 12/18頁(yè) |
| 文件大?。?/td> | 317K |
| 代理商： | POWERPC 440 |
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PowerPC 440 Core
09/21/1999
Page 12 of 18
Timers
The PPC440 contains a 64-bit time base and three timers: the Decrementer (DEC), the Fixed Interval
Timer (FIT), and the WatchDog Timer (WDT). The time base counter increments synchronously with the
CPU clock or an external clock source. The three timers are synchronous with the time base.
The DEC is a 32-bit register that decrements at the time base increment rate. The user loads the DEC
register with a value to create the desired delay. When the register reaches zero, the timer stops
decrementing and generates a decrementer interrupt. Optionally, the DEC can be programmed to auto-
reload the value last written to the DEC auto-reload register, after which the DEC continues to decrement.
The FIT generates periodic interrupts based on one of four selectable bits in the time base. When the
selected bit changes from 0 to 1, the PPC440 generates a FIT exception.
The watchdog timer provides a periodic critical-class interrupt based on a selected bit in the time base.
This interrupt can be used for system error recovery in the event of software or system lockups. Users may
select one of four time periods for the interval and the type of reset generated if the watchdog timer
expires twice without an intervening clear from software. If enabled, the watchdog timer generates a reset
unless an exception handler updates the watchdog timer status bit before the timer has completed two of
the selected timer intervals.
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