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參數(shù)資料
| 型號(hào)： | PowerPC 440 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC PowerPC Embedded Processor Cores(32位 RISC PowerPC 嵌入式處理器) |
| 中文描述： | 32位RISC PowerPC嵌入式處理器內(nèi)核（RISC的32位的PowerPC嵌入式處理器） |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大?。?/td> | 317K |
| 代理商： | POWERPC 440 |
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PowerPC 440 Core
09/21/1999
Page 3 of 18
Figure 1. Example PPC440 Core + ASIC
Specifications
Performance
(Dhrystone 2.1)
Frequency
1000 MIPS @ 555MHz (est.), Nominal silicon, 1.8V, 55
°
C
720 MIPS @ 400MHz (est.), Slow silicon, 1.65V, 85
°
C
0 – 400MHz , Slow silicon, 1.65V, 85
°
C
555MHz nominal
2.5mW / MHz @ 1.8V (est.), hard core with 32KI / 32KD caches
32-bit PowerPC Book E compliant, application code compatible with
all PowerPC processors
4.0 mm
2
for CPU only (est.)
0-64KB, 32-way to 128-way associative
0.18 μm CMOS copper technology
0.12 μm L
eff
, 4 levels of metal
1.8 Volts
5.5M, hard core with 32KI / 32KD caches
-40
°
C to 125
°
C, 1.6V to 1.9V
Up to 6.4 GB/sec via three 128-bit, 200MHz CoreConnect bus
interfaces
Power Dissipation
Architecture
Die Size
Caches
Technology
Power Supply
Transistors
Operating Range
Data Bandwidth
Table 1- 440 CPU Core Specifications
Embedded Design Support
The PPC440 Core, as a member of the PowerPC 400 Family, is supported by the IBM PowerPC
Embedded Tools
TM
program, in which over 80 third party vendors have combined with IBM to provide a
complete tools solution. Development tools for the PPC440 include C/C++ compilers, debuggers, bus
functional models, hardware/software co-simulation environments, and real-time operating systems. As
part of the tools program, IBM maintains a complete set of development tools by offering the High C/C++
Compiler, RISCWatch
TM
debugger with RISCTrace
TM
trace interface, VHDL and Verilog simulation
models and a PPC440 Core Superstructure development kit.
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