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參數(shù)資料
| 型號： | PowerPC 440 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC PowerPC Embedded Processor Cores(32位 RISC PowerPC 嵌入式處理器) |
| 中文描述： | 32位RISC PowerPC嵌入式處理器內(nèi)核（RISC的32位的PowerPC嵌入式處理器） |
| 文件頁數(shù)： | 8/18頁 |
| 文件大小： | 317K |
| 代理商： | POWERPC 440 |
PowerPC 440 Core
09/21/1999
Page 8 of 18
Figure 4 – Two Examples of Cache Partitioning
I-Cache Speculative Pre-fetching
The I-Cache utilizes a programmable speculative pre-fetch mechanism to enhance performance. Software
can enable up to three additional lines to be speculatively pre-fetched, using a burst protocol, upon any
instruction cache miss. When this mode is enabled, the I-Cache controller will automatically inspect the I-
Cache on a miss to see if any of up to the next three lines are also misses. If so, the hardware will present
a burst request to the PLB immediately after the original line fill request. This speculative burst request
takes advantage of the throughput capability of standard memory architectures such as SDRAM and
brings in anticipated subsequent instructions after a miss. Furthermore, if the instruction stream branches
away from the lines which are being speculatively filled, the burst request which is filling the speculative
lines can be abandoned in the middle, and a new fill request at the branch target location immediately
initiated. There is a programmable "threshold" to determine when to abandon a speculative line fill that
may have been in progress at the time of a branch redirection. This threshold designates how many
doublewords of the speculative cache line must be received to
not
abandon a current line fill. In this
fashion, the speculative pre-fetch mechanism can be carefully tailored to provide optimum performance
for specific applications and memory subsystems.
D-Cache Line Fills
The D-Cache contains three line fill buffers and can queue up to four load misses to three separate cache
lines. The PPC440 will then execute past these load misses, until the queue is full or the pipes are held
waiting for a load value. The D-Cache controller places the target word on the bypass path as the fill
buffer captures data words off the PLB. Additional requests of the cache line held in the fill buffer are
also forwarded directly to the operand registers in the execute unit.
D-Cache Non-cacheable Store Gathering
The D-Cache “gathers” up to 16 bytes for non-cacheable, write-through, and w/o allocate stores, and will
burst the quadword to the PLB for fast writes to non-cacheable memory.
D-Cache Write-Back and Write-Through Modes
The D-Cache supports write-back or write-through mode. In write-back mode, store hits are written to the
cache and not to main memory. Main memory is later modified if and when the line is flushed from the
cache. In write-through mode, the data cache controller writes main memory for store misses as well as
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