
STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER  WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
288
Table 52
- SBI ADD BUS Timing (Figure 96)
Symbol
Description
Min
Max
Units
SREFCLK Frequency (See Note 6)
19.44
-50 ppm
19.44
+50 ppm
MHz
SREFCLK Duty Cycle
40
60
%
tS
SBIADD
All SBI ADD BUS Inputs Set-Up
Time to SREFCLK (See Note 1)
4
ns
tH
SBIADD
All SBI ADD BUS Inputs Hold Time
to SREFCLK (See Note 2)
0.75
ns
tP
SBIADD
SREFCLK to SAJUST_REQ Valid
(See Notes 3 and 4)
2
20
ns
tZ
SBIADD
SREFCLK to SAJUST_REQ Tristate
(See Note 5)
2
20
ns
Notes on SBI Input Timing:
1. When a set-up time is specified between an input and a clock, the set-up
time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4
Volt point of the clock.
2. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
3. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
4. Maximum and minimum output propagation delays are measured with a 100
pF load on all the outputs.
5. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the
reference signal to the point where the total current delivered through the
output is less than or equal to the leakage current.
6. Note that in Transparent VT mode this clock must be connected to
LREFCLK.  In this case, the more stringent specification of +/- 20ppm
applies.