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STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
224
Table 29
- E1 Channel Associated Signaling bits
TS#16[7:4]
TS#16[3:0]
PP
RRRR
RRRR
00
ABCD1
ABCD16
00
ABCD2
ABCD17
00
ABCD3
ABCD18
00
ABCD4
ABCD19
00
ABCD5
ABCD20
00
ABCD6
ABCD21
00
ABCD7
ABCD22
00
ABCD8
ABCD23
00
ABCD9
ABCD24
00
ABCD10
ABCD25
00
ABCD11
ABCD26
00
ABCD12
ABCD27
00
ABCD13
ABCD28
00
ABCD14
ABCD29
00
ABCD15
ABCD30
C0
E1 tributary asynchronous timing is compensated via the V3 octet. E1 tributary
link rate adjustments are optionally passed across the SBI via the V4 octet. E1
tributary alarm conditions are optionally passed across the SBI bus via the link
rate octet in the V4 location.
In synchronous mode the E1 tributary mapping is fixed to that shown in Table 28
and rate justifications are not possible using the V3 octet. The clock rate
information within the link rate octet in the V4 location is not used in synchronous
mode.
Note that ITU-T G.747 mutiplexed E1 streams are not supported over the SBI
interface. This E1 mode of operation is restricted to using the serial clock and
data or H-MVIP system interfaces.
DS3 Tributary Mapping
Table 30 shows a DS3 tributary mapped within the first synchronous payload
envelope SPE1. The V5 indicator pulse identifies the V5 octet. The DS3 framing
format does not follow an 8KHz frame period so the floating DS3 multi-frame
located by the V5 indicator, shown in heavy border grey region in Table 30, will
jump around relative to the H1 frame on every pass. In fact the V5 indicator will
often be asserted twice per H1 frame, as is shown by the second V5 octet in
Table 30. The V5 indicator and payload signals indicate negative and positive