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STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
256
13.4 Telecom ADD Bus Interface Timing
Figure 65 shows the function of the telecom ADD bus signals in AU3 mode.
Data on LADATA[7:0] is updated on the rising edge of LREFCLK. The LAC1
input is sampled on the rising edge of LREFCLK and aligns all devices on the
ADD bus by marking the first C1 byte of the first STS-1 in every fourth STS-3
transport envelope. LAC1 pulses every fourth STS-3 to indicate tributary
multiframe alignment on the ADD bus. The bytes forming the three STS-1
synchronous payload envelopes are identified when the LAPL signal is high. The
LAC1J1V1 signal pulses high, while LAPL is set low, to mark the C1 byte of the
first STS-1 in every frame of the STS-3 transport envelope. The LAC1J1V1
signal is high when the LAPL signal is high to mark every J1 byte of each of the
three STS-1 SPEs. The three STS-1 SPEs are fixed at two different alignments
to the STS-3 transport envelope. The first is shown in Figure 65 in which the J1
bytes follow immediately after the C1 bytes. The second alignment is at SPE
pointer location zero where the J1 bytes follow immediately after the H3 bytes.
The LAC1 signal is updated on the rising edge of LREFCLK. It is output during
when the TEMUX is outputing valid tributary data onto the ADD bus. It is
asserted high for all bytes making up a tributary and is asserted low during
overhead bytes.
Figure 65
- Output Bus Timing - Locked STS-1 SPEs / AU3 VCs
LREFCLK
LAC1
LAC1J1V1
LAPL
Implicit location
of STS-1 SPE
J1 bytes
V1 byte VT #1, STS-1 #1
V1 byte VT #1, STS-1 #2
V1 byte VT #1, STS-1 #3
LADATA[7:0]
A2 C1 C1 C1
H1 H1 H2 H2 H2 H3
H3
H1
H3
No stuff events possible
V5 byte VT #1, STS-1 #2
J1 J1 J1 V1 V1 V1 V1 V1 V1 V1
V5
V1 bytes VT #2
J2
J2 byte VT #1, STS-1 #1
LAOE