
STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER  WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
120
Clock Master: Clear Channel mode has no frame alignment therefore no frame
alignment is indicated to the upstream device. ECLK[x] is a continuous clock at
1.544Mb/s for T1 links or 2.048Mb/s for E1 links.
Figure 19
- Clock Slave: EFP Enabled
TJAT
FIFO
T1-XBAS/E1-TRAN
 BasicTransmitter:
Frame Generation,
Alarm Insertion,
Signaling Insertion,
Trunk Conditioning
Line Coding 
ESIF
Egress
System
Interface 
TRANSMITTER 
Transmit CLK[1:28]
Transmit Data[1:28]
ED[1:28]
EFP[1:28] 
CEFP
CECLK
TJAT
Digital PLL
Inputs Timed
to CECLK
In Clock Slave: EFP Enabled mode, the egress interface is clocked by the
common egress clock, CECLK.  The transmitter is either frame-aligned or
superframe-aligned to the common egress frame pulse, CEFP, via the CEMFP
bit in the Master Egress Slave Mode Serial Interface Configuration register.
EFP[x] is configurable to indicate the frame alignment or the superframe
alignment of ED[x].  CECLK can be enabled to be either a 1.544 MHz clock for
T1 links or a 2.048 MHz clock for T1 and E1 links.  The CECLK2M bit in the
Master Egress Slave Mode Serial Interface Configuration register selects the
2.048MHz clock for T1 operation.
Figure 20
- Clock Slave: External Signaling
TJAT
FIFO
T1-XBAS/E1-TRAN
 BasicTransmitter:
Frame Generation,
Alarm Insertion,
Signaling Insertion,
Trunk Conditioning
Line Coding 
ESIF
Egress
System
Interface 
TRANSMITTER 
Transmit Data[1:28]
ED[1:28]
ESIG[1:28] 
CEFP
CECLK
TJAT
Digital PLL
Transmit CLK[1:28]
Inputs Timed
to CECLK
In Clock Slave: External Signaling mode, the egress interface is clocked by the
common egress clock, CECLK.  The transmitter is either frame-aligned or
superframe-aligned to the common egress frame pulse, CEFP, via the CEMFP
bit in the Master Egress Slave Mode Serial Interface Configuration register.  The
ESIG[x] signal contains the robbed-bit signaling data to be inserted into Transmit