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STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
6
Provides a digital phase locked loop for generation of a low jitter transmit
clock.
Provides a FIFO buffer for jitter attenuation and rate conversion in the
transmitter.
Automatically generates and transmits DS-1 performance report messages to
ANSI T1.231and ANSI T1.408 specifications.
Supports the alternate ESF CRC-6 calculation for Japanese applications.
A pseudo-random sequence user selectable from 2
11
–1, 2
15
–1 or 2
20
–1,
may be inserted into the T1 stream in either the ingress or egress directions.
The pseudo-random sequence can be inserted into the entire T1 or any
combination of DS0s within the framed T1.
Line side interface is through either DS3 Interface via the M13 multiplex or
the SONET/SDH Add bus via the VT1.5, TU-11, VT2 or TU-12 mapper.
System side interface is either serial clock and data, MVIP or SBI bus.
Each one of 21 E1 transmitter sections:
Provides a FIFO buffer for jitter attenuation and rate conversion in the
transmit path.
Transmits G.704 basic and CRC-4 multiframe formatted E1.
Supports unframed mode and framing bit, CRC, or data link by-pass.
Provides signaling insertion, programmable idle code substitution, digital
milliwatt code substitution, and data inversion on a per channel basis.
Provides trunk conditioning which forces programmable trouble code
substitution and signaling conditioning on all channels or on selected
channels.
Provides a digital phase locked loop for generation of a low jitter transmit
clock.
A pseudo-random sequence user selectable from 2
11
–1, 2
15
–1 or 2
20
–1,
may be inserted into the E1 stream in either the ingress or egress directions.
The pseudo-random sequence can be inserted into the entire E1 or any
combination of timeslots within the framed E1.