- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄378055 > PM73121-RI (PMC-SIERRA INC) AAL1 Segmentation And Reassembly Processor PDF資料下載
參數(shù)資料
| 型號(hào)： | PM73121-RI |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | AAL1 Segmentation And Reassembly Processor |
| 中文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PQFP240 |
| 封裝： | QFP-240 |
| 文件頁(yè)數(shù)： | 82/223頁(yè) |
| 文件大?。?/td> | 2300K |
| 代理商： | PM73121-RI |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)當(dāng)前第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)
PM73121AAL1gator II
PMC-Sierra, Inc.
L
PMC-980620
,VVXH
AAL1 SAR Processor
Data Sheet
35235,(7$5<$1'&21),'(17,$/7230&6,(55$,1&$1')25,76&86720(56,17(51$/86(
3.6.5
Counters and Sticky Bits
The RALP sets sticky bits for overrun, underrun, pointer mismatch, resume, SRTS underrun,
SRTS resume, and other conditions. As with all registers, the sticky bits are located in the external
RAM. They are set by the AAL1gator II and must be cleared by the microprocessor. Sticky bits
provide a history of events that have occurred. Since these bits can be set with every cell, it is bet-
ter to use the counters for statistics gathering purposes. The AAL1gator II increments the counters
for incorrect SNs, incorrect SNPs, cells received, underflows, overflows, dropped cells, misin-
serted cells, lost cells, pointer parity errors, and pointer mismatches. The transfer status bits can
be used to detect that a clear was overwritten by toggling transfer bit 15 with each clear of the sta-
tus bits and then reading the value immediately thereafter. Refer to
“R_ERROR_STKY Word
Format” on page 158
for a description of sticky bits.
3.6.6
OAM Cells
When an OAM cell arrives, the RALP stores it in the OAM queue. The RALP notifies the micro-
processor of the arrival of OAM cells by generating an interrupt. The interrupt is cleared when the
CLR_RX_OAM_LATCH (refer to
“CMDREG Word Format” on page 165
) is set. The micro-
processor reads the OAM cells from the OAM queue. The microprocessor maintains the OAM_
HEAD value. The RALP maintains the OAM_TAIL value. The AAL1gator II also checks the
CRC-10 of the cell and records the results in the receive buffer in the CRC_10_PASS parameter
(refer to
“R_OAM_CELL_n Format” on page 163
).
3.6.7
Interrupt Handling
The AAL1gator II uses the following algorithm to handle interrupts:
1. An internal register called the command register (refer to
section 7.9 “CMDREG (Command
Register)” on page 165
) handles interrupts. This command register has an OAM_INT_MASK
bit. The microprocessor can access the command register by asserting the ADDR17 pin, the
/PROC_CS signal, and either the /PROC_RD or the /PROC_WR signal.
2. At the end of an OAM cell, the RALP generates an interrupt to the microprocessor. If the
mask bit is set, the RALP does not present the interrupt to the interrupt pin.
3. At the end of any cell (either an OAM or data cell), the head and tail pointers of the OAM
queue table are compared. If they do not match (that is, if there are cells in the OAM FIFO),
the RALP sets the interrupt latch.
3.7
The RFTC moves data bytes from the receive frame buffer to the appropriate timeslot of the
appropriate line. It must perform a timeslot-to-queue translation for each timeslot by reading the
receive channel-to-queue table (refer to
section 7.8.6 “R_CH_TO_QUEUE_TBL” on page 148
).
The RFTC outputs data to the external T1 or E1 framer device. For structured data, the RFTC
Receive Frame Transfer Controller (RFTC)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PM73122 | 32 LINK CES/DBCES AAL1 SAR PROCESSOR |
| PM73122-BI | 32 LINK CES/DBCES AAL1 SAR PROCESSOR |
| PM73123 | 8 LINK CES/DBCES AAL1 SAR |
| PM73123-PI | 8 LINK CES/DBCES AAL1 SAR |
| PM73124 | 4 Link CES/DBCES AAL1 SAR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM73122 | 制造商:PMC 制造商全稱:PMC 功能描述:32 LINK CES/DBCES AAL1 SAR PROCESSOR |
| PM73122-BI | 制造商:PMC 制造商全稱:PMC 功能描述:32 LINK CES/DBCES AAL1 SAR PROCESSOR |
| PM73122-BIP | 制造商:PMC-Sierra 功能描述:AAL1GATOR32 EOL270906 |
| PM73122-BI-P | 制造商:PMC-Sierra 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。