![](http://datasheet.mmic.net.cn/330000/PM73121_datasheet_16444365/PM73121_196.png)
PMC-Sierra, Inc.
PM73121AAL1gator II
L
PMC-980620
,VVXH
AAL1 SAR Processor
Data Sheet
35235,(7$5<$1'&21),'(17,$/7230&6,(55$,1&$1')25,76&86720(56,17(51$/86(
Tp - Tch
max
- Rs -10
≥
0.5 ns
A 2.5% duty cycle CMOS clock source at 38.88 MHz has a Tch
min
of 12.2 ns and a Tch
max
of
13.5 ns at 2.5 V.
A rise/fall time of 0.5 ns (from 20-80%) results in a gain of 0.33 ns at 1.5 V and would change
Tch
min
to 12.53 ns.
A rise/fall time of 2 ns (from 20-80%) results in a gain of 1.33 ns at 1.5 V and would change
Tch
max
to 14.83 ns.
Replacing Tch
min
and Tch
max
in the equations above gives:
Rs
≥
8.5 + 4.3 -12.53
≥
0.27 ns
Rs
≤
25.7 - 14.83 - 10 - 0.5
≤
0.37 ns
Referring to
Table 24 on page 175
, selecting a 33
resistor would meet both of these
requirements.
In summary, a possible solution when using an SRAM with 8 ns setup is to use a 2.5% duty cycle
CMOS clock (with a minimum rise/fall time of 0.5 ns and a maximum rise/fall time of 2 ns) and a
33
series resistor. To improve margin, either the duty cycle needs to be tightened or the
maximum rise time needs to be reduced, which would allow a larger resistor.
8.6.5
Layout
The delay information provided assumes a 15 pF load on the /MEM_WE signals that have one
load and a 30 pf load on the MEM_DATA outputs that have two loads. The trace capacitance is
approximately 2 pF per inch and the input pin capacitance is about 7 pF. Therefore, the SRAM
trace lengths should be approximately four inches long.
Also, the series resistor should be placed as close as possible to the source pin.