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| 型號(hào)： | PE3337-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, UUC52 |
| 封裝： | WAFER-52 |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大?。?/td> | 315K |
| 代理商： | PE3337-99 |
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PE3337
Advance Information
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 5 of 13
Table 5. DC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified. All parameters at TA = 85° C guaranteed through wafer probe.
Temperature performance verified on sample basis during lot evaluation.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IDD
Operational supply current;
Prescaler disabled
Prescaler enabled
VDD = 2.85 to 3.15 V
10
24
31
mA
Digital Inputs: All except FR, FIN (all digital inputs have 70k ohm pull-up resistors)
VIH
High level input voltage
VDD = 2.85 to 3.15 V
0.7 x VDD
V
VIL
Low level input voltage
VDD = 2.85 to 3.15 V
0.3 x VDD
V
IIH
High level input current
VIH = VDD = 3.15 V
+70
A
IIL
Low level input current
VIL = 0, VDD = 3.15 V
-1
A
Reference Divider input: FR
IIHR
High level input current
VIH = VDD = 3.15 V
+100
A
IILR
Low level input current
VIL = 0, VDD = 3.15 V
-100
A
Counter and phase detector outputs: fc, fp.
VOLD
Output voltage LOW
Iout = 6 mA
0.4
V
VOHD
Output voltage HIGH
Iout = -3 mA
VDD - 0.4
V
Lock detect outputs: CEXT, LD
VOLC
Output voltage LOW, CEXT
Iout = 100
0.4
V
VOHC
Output voltage HIGH, CEXT
Iout = -100
VDD - 0.4
V
VOLLD
Output voltage LOW, LD
Iout = 6 mA
0.4
V
Table 6. AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified. All parameters at TA = 85° C guaranteed through wafer probe.
Temperature performance verified on sample basis during lot evaluation.
Symbol
Parameter
Conditions
Min
Max
Units
Control Interface and Latches (see Figures 1and 3)
fClk
CLOCK Serial data clock frequency
(Note 1)
10
MHz
tClkH
CLOCK Serial clock HIGH time
30
ns
tClkL
CLOCK Serial clock LOW time
30
ns
tDSU
DATA set-up time after CLOCK rising edge
10
ns
tDHLD
DATA hold time after CLOCK rising edge
10
ns
tPW
S_WR pulse width
30
ns
tCWR
CLOCK rising edge to S_WR rising edge.
30
ns
tCE
CLOCK falling edge to E_WR transition
30
ns
tWRC
S_WR falling edge to CLOCK rising edge.
30
ns
tEC
E_WR transition to CLOCK rising edge
30
ns
tMDO
MSEL data out delay after FIN rising edge
CL = 12 pf
8
ns
Note 1:
Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
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