- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98051 > PE3337-99 (PEREGRINE SEMICONDUCTOR CORP) PHASE LOCKED LOOP, UUC52 PDF資料下載
參數(shù)資料
| 型號(hào)： | PE3337-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, UUC52 |
| 封裝： | WAFER-52 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 315K |
| 代理商： | PE3337-99 |
PE3337
Advance Information
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 3 of 13
Pad #
X
Y
Name
Interface Mode
Type
Description
M5
Direct
Input
M Counter bit5
18
-1188
-600
GND_C
Both
GND
19
-1188
-750
GND_E
Both
GND
CLOCK
Serial
Input
Clock input. Data is clocked serially into either the 20-bit primary
register (E_WR “l(fā)ow”) or the 8-bit enhancement register (E_WR
“high”) on the rising edge of CLOCK.
20
-1188
-900
M6
Direct
Input
M Counter bit6
21
-900
-1188
M7
Direct
Input
M Counter bit7
22
-750
-1188
M8
Direct
Input
M Counter bit8 (MSB)
23
-600
-1188
A0
Direct
Input
A Counter bit0
24
-450
-1188
BMODEX
Both
Input
Selects direct interface mode (DMODE=1) or serial interface mode
(DMODE=0)
25
-300
-1188
VDD_E
Both
(Note 1)
Same as Pad 1
26
-150
-1188
VDD_P
Both
(Note 1)
Same as Pad 1
E_WR
Serial
Input
Enhancement register write enable. While E_WR is “high”, DATA
can be serially clocked into the enhancement register on the rising
edge of CLOCK.
27
0
-1188
A1
Direct
Input
A Counter bit1.
28
150
-1188
A2
Direct
Input
A Counter bit2
29
300
-1188
A3
Direct
Input
A Counter bit3 (MSB)
30
450
-1188
FIN
Both
Input
RF prescaler input from the VCO. 3.0 GHz max frequency
31
600
-1188
FINX
Both
Input
Prescaler complementary input. A bypass capacitor should be
placed as close as possible to this pin and be connected in series
with a 50
resistor directly to the ground plane.
32
750
-1188
GND_P
Both
GND
33
900
-1188
GND_E
Both
GND
34
1188
-900
GND_0
Both
GND
35
1188
-750
CPSEL
Both
Input
Charge pump select. “High” enables the charge pump and disables
pins PD_U and PD_D by forcing them “l(fā)ow”. A “l(fā)ow” Tri-states the
CP and enables PD_U and PD_D.
36
1188
-600
VDD_O
Both
(Note 1)
Same as Pad 1
37
1188
-450
DOUT
Serial
Output
Data Out. The Main Counter output, R Counter output, or dual
modulus prescaler select (MSEL) can be routed to DOUT through
enhancement register programming.
38
1188
-300
VDD_E
Both
(Note 1)
Same as Pad 1
39
1188
-150
CP
Both
Output
Charge pump output. Selected when CPSEL = “1”. Tristate when
CPSEL = “Low”.
40
1188
0
VDD_O
Both
(Note 1)
Same as Pad 1
41
1188
150
GND_O
Both
GND
42
1188
300
PD_DX
Both
Output
PD_D pulses down when fp leads fc.
43
1188
450
PD_UX
Both
PD_U pulses down when fc leads fp.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PE33631MLIAA | PHASE DETECTOR, QCC64 |
| PE33631MLIAA-Z | PHASE DETECTOR, QCC64 |
| PG001M | STEPPER MOTOR CONTROLLER, 0.015 A, PDIP16 |
| PGA308AIDRKR | SPECIALTY ANALOG CIRCUIT, PQCC10 |
| PGA308AIDRKT | SPECIALTY ANALOG CIRCUIT, PQCC10 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PE33383 | 制造商:PASTERNACK 制造商全稱:Pasternack Enterprises, Inc. 功能描述:CABLE ASSEMBLY RG316/U BNC MALE TO TNC MALE |
| PE3339 | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:3.0 GHz Integer-N PLL for Low Phase Noise Applications |
| PE33399 | 制造商:PASTERNACK 制造商全稱:Pasternack Enterprises, Inc. 功能描述:CABLE ASSEMBLY RG11A/U 75 OHM BNC MALE TO 75 OHM BNC MALE |
| PE33399LF | 制造商:PASTERNACK 制造商全稱:Pasternack Enterprises, Inc. 功能描述:CABLE ASSEMBLY RG11A/U 75 OHM BNC MALE TO 75 OHM BNC MALE(LEAD FREE) |
| PE3339EK | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:3.0 GHz Integer-N PLL for Low Phase Noise Applications |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。