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參數(shù)資料
| 型號： | PE3337-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, UUC52 |
| 封裝： | WAFER-52 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 315K |
| 代理商： | PE3337-99 |
PE3337
Advance Information
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0150~00A
| | UTSi CMOS RFIC SOLUTIONS
Page 6 of 13
Table 7. AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified. All parameters verified on sample basis during lot evaluation.
Symbol
Parameter
Conditions
Min
Max
Units
Main Divider (Including Prescaler)
FIN
Operating frequency
500
3000
MHz
PFin
Input level range
External AC coupling
-5
5
dBm
Main Divider (Prescaler Bypassed)
F
Operating frequency
50
300
MHz
PFin
Input level range
External AC coupling
-5
5
dBm
Reference Divider
FR
Operating frequency
(Note 3)
100
MHz
PFr
Reference input power
Single-ended input, (Note 1)
-2
dBm
Phase Detector
fc
Comparison frequency
(Note 3)
20
MHz
Note 1:
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p.
Note 2:
Parameter is guaranteed through characterization only and is not tested.
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