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參數(shù)資料
| 型號(hào)： | PE3337-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, UUC52 |
| 封裝： | WAFER-52 |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大?。?/td> | 315K |
| 代理商： | PE3337-99 |
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PE3337
Advance Information
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0150~00A
| | UTSi CMOS RFIC SOLUTIONS
Page 4 of 13
Pad #
X
Y
Name
Interface Mode
Type
Description
44
1188
600
VDD_O
Both
(Note 1)
Same as Pad 1
45
1188
750
VDD_E
Both
(Note 1)
Same as Pad 1
46
1188
900
CEXT
Both
Output
Logical “NAND” of PD_U and PD_D, passed through an on-chip, 2
k
series resistor. Connecting CEXT to an external capacitor will
low pass filter the input to the inverting amplifier used for driving
LD.
47
900
1188
GND_O
Both
GND
48
750
1188
GND_E
Both
GND
49
600
1188
GND_R
Both
GND
50
450
1188
FR
Both
Input
Reference frequency input
51
300
1188
ENHX
Both
Output, OD
Enhancement mode. When asserted low (“0”), enhancement
register bits are functional.
52
150
1188
LD
Serial
Output
Lock detect output, the open-drain logical inversion of CEXT. When
the loop is locked, LD is high impedance; otherwise LD is a logic
low (“0”).
Note 1:
VDD pads 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
Note 2:
All digital input pins have 70 k
pull-down resistors to ground.
Table 2. Absolute Maximum Ratings
Symbol
Parameter/Conditions
Min
Max
Units
VDD
Supply voltage
-0.3
4.0
V
VI
Voltage on any input
-0.3
VDD
+
0.3
V
II
DC into any input
-10
+10
mA
IO
DC into any output
-10
+10
mA
Tstg
Storage temperature
range
-65
150
°C
Table 3. Operating Ratings
Symbol
Parameter/Conditions
Min
Max
Units
VDD
Supply voltage
2.85
3.15
V
TA
Operating ambient
temperature range
-40
85
°C
Table 4. ESD Ratings
Symbol
Parameter/Conditions
Level
Units
VESD
ESD voltage (Human Body
Model) – Note 1
1000
V
Note 1:
Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
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