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參數(shù)資料
| 型號： | PE3337-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, UUC52 |
| 封裝： | WAFER-52 |
| 文件頁數(shù)： | 13/13頁 |
| 文件大?。?/td> | 315K |
| 代理商： | PE3337-99 |
PE3337
Advance Information
PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 9 of 13
Figure 3. Serial Interface Mode Timing Diagram
Enhancement Register
The functions of the enhancement register bits are shown below. All bits are active high. Operation is
undefined if more than one output is sent to
DOUT.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Reserved**
Bit 1
Reserved**
Bit 2
fp output
Drives the M counter output onto the DOUT output.
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming.
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the DOUT output.
Bit 6
fc output
Drives the R counter output onto the DOUT output
Bit 7
Reserved**
** Program to 0
t
t
DSU
t
ClkH
t
ClkL
t
CWR
t
PW
t
WRC
t
EC
t
CE
E_WR
DATA
CLOCK
S_WR
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