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參數(shù)資料
| 型號： | PE3337-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, UUC52 |
| 封裝： | WAFER-52 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 315K |
| 代理商： | PE3337-99 |
PE3337 Die
Advance Information
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0150~00A
| | UTSi CMOS RFIC SOLUTIONS
Page 2 of 13
Figure 2. Pad Configuration
Table 1. Pad Descriptions
Pad #
X
Y
Name
Interface Mode
Type
Description
1
0
1188
VDD_R
Both
(Note 1)
Power supply input. Input may range from 2.85 V to 3.15 V.
Bypassing recommended.
2
-150
1188
VDD_E
Both
(Note 1)
Same as Pad 1
3
-300
1188
R0
Direct
Input
R Counter bit0
4
-450
1188
R1
Direct
Input
R Counter bit1
5
-600
1188
R2
Direct
Input
R Counter bit2
6
-750
1188
R3
Direct
Input
R Counter bit3
7
-900
1188
GND_E
Both
GND
8
-1188
900
R4
Direct
Input
R Counter bit4
9
-1188
750
R5
Direct
Input
R Counter bit5 (MSB)
10
-1188
600
M0
Direct
Input
M Counter bit0
11
-1188
450
M1
Direct
Input
M Counter bit1
12
-1188
300
VDD_E
Both
(Note 1)
Same as Pad 1
13
-1188
150
VDD_C
Both
(Note 1)
Same as Pad 1
14
-1188
0
M2
Direct
Input
M Counter bit2
15
-1188
-150
M3
Direct
Input
M Counter bit3
S_WR
Serial
Input
Frequency register load enable input. Buffered data is transferred
to the frequency register on S_WR rising edge.
16
-1188
-300
M4
Direct
Input
M Counter bit4
17
-1188
-450
DATA
Serial
Input
Binary serial data input. Data is entered LSB first, and is clocked
serially into the 20-bit frequency control register (E_WR “l(fā)ow”) or
the 8-bit enhancement register (E_WR “high”) on the rising edge of
CLOCK.
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