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參數(shù)資料
| 型號(hào)： | PE3337-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, UUC52 |
| 封裝： | WAFER-52 |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大?。?/td> | 315K |
| 代理商： | PE3337-99 |
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PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 1 of 13
Product Description
Figure 1. Block Diagram
ADVANCE INFORMATION
PE3337DIE
3.0 GHz Integer-N PLL
Features
3.0 GHz operation
÷10/11 dual modulus prescaler
Phase detector output
Serial interface or hardwired
programmable
Ultra-low phase noise
Die Form
Peregrine’s PE3337 is a high-performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The
device is designed for superior phase noise performance
while providing an order of magnitude reduction in
current consumption, when compared with existing
commercial space PLL’s. The device is offered in
electrically screened die form for MCM/Hybrid
applications.
The PE3337 features a ÷10/11 dual modulus prescaler,
counters, and a phase comparator as shown in Figure 1.
Counter values are programmable through a serial
interface, and can also be directly hard wired.
Fabricated in Peregrine’s patented UTSi (Ultra Thin
Silicon) CMOS technology, the PE3337 offers excellent
RF performance and intrinsic radiation tolerance.
F
IN
Prescaler
10 / 11
Main
Counter
20-Bit
Frequency
Register
M(8:0)
A(3:0)
R(5:0)
19*
20
R Counter
F
R
Phase
Detector
6
13
Serial
Control
PD_U
PD_D
3
MSEL
f
p
f
c
Direct
Control
* prescaler bypass not available in Direct mode
LD
Cext
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