參數(shù)資料
型號： PD6710
廠商： Intel Corp.
英文描述： ISA-to-PC-Card (PCMCIA) Controllers
中文描述： ISA -到- PC卡（PCMCIA）的控制器
文件頁數(shù)： 4/138頁
文件大小： 723K
代理商： PD6710
PD6710/
’
22
—
ISA-to-PC-Card (PCMCIA) Controllers
4
Datasheet
8.3
8.4
8.5
8.6
8.7
Memory Window Mapping Registers
...............................................................64
9.1
System Memory Map 0
–
4 Start Address Low.....................................................64
9.2
System Memory Map 0
–
4 Start Address High....................................................65
9.3
System Memory Map 0
–
4 End Address Low......................................................66
9.4
System Memory Map 0
–
4 End Address High .....................................................66
9.5
Card Memory Map 0
–
4 Offset Address Low.......................................................67
9.6
Card Memory Map 0
–
4 Offset Address High ......................................................68
Extension Registers
................................................................................................70
10.1
Misc Control 1 .....................................................................................................70
10.2
FIFO Control .......................................................................................................72
10.3
Misc Control 2 .....................................................................................................72
10.4
Chip Information..................................................................................................74
10.5
ATA Control.........................................................................................................75
10.6
Extended Index...................................................................................................77
10.7
Extended Data ....................................................................................................77
10.7.1 Data Mask 0
–
1.......................................................................................78
10.7.2 Extension Control 1 (PD6722 only, formerly DMA Control) ...................78
10.7.3 Maximum DMA Acknowledge Delay (PD6722 only)..............................79
10.7.4 External Data (PD6722 only, Socket A, Index 2Fh)...............................81
10.7.5 External Data (PD6722 only, Socket A, Index 6Fh)...............................82
10.7.6 Extension Control 2 (PD6722 only)........................................................83
Timing Registers
......................................................................................................84
11.1
Setup Timing 0
–
1 ...............................................................................................84
11.2
Command Timing 0
–
1.........................................................................................85
11.3
Recovery Timing 0
–
1 ..........................................................................................86
ATA Mode Operation
..............................................................................................88
Using GPSTB Pins for External Port Control
(PD6722 only)
91
13.1
Control of GPSTB Pins .......................................................................................91
13.2
Example Implementations of GPSTB-Controlled Read and Write Ports.............93
13.3
GPSTB in Suspend Mode...................................................................................94
VS1# and VS2# Voltage Detection
....................................................................95
DMA Operation (PD6722 only)
............................................................................97
15.1
DMA Capabilities of the PD6722.........................................................................97
15.2
DMA-Type PC Card Cycles ................................................................................97
15.3
ISA Bus DMA Handshake Signal........................................................................98
15.4
Configuring the PD6722 Registers for a DMA Transfer......................................98
15.4.1 Programming the DMA Request Pin from the Card...............................98
15.4.2 Configuring the Socket Interface for I/O.................................................99
System I/O Map 0
–
1 Start Address High ............................................................60
System I/O Map 0
–
1 End Address Low ..............................................................60
System I/O Map 0
–
1 End Address High .............................................................61
Card I/O Map 0
–
1 Offset Address Low ...............................................................62
Card I/O Map 0
–
1 Offset Address High ..............................................................62
9.0
10.0
11.0
12.0
13.0
14.0
15.0
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